ESD Series
By Steven H. Voldman

Electrical Overstress (EOS): Devices, Circuits and Systems

ISBN: 9781118511886

September 2013

ESD Basics: From Semiconductor Manufacturing to Product Use

ISBN: 9780470979716

October 2012

ESD: Design and Synthesis

ISBN: 9780470685716

March 2011

ESD: Failure Mechanisms and Models

ISBN: 9780470511374

July 2009

Latchup

ISBN: 9780470016428

December 2007

ESD: RF Technology and Circuits

ISBN: 9780470847558

September 2006

ESD: Circuits and Devices

ISBN: 9780470847541

November 2005

ESD: Physics and Devices

ISBN: 9780470847534

September 2004

Upcoming titles:

ESD: Test and Characterization

The ESD Handbook

ESD: Analog Circuits and Design

This edition first published 2014

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Library of Congress Cataloging-in-Publication Data

Voldman, Steven H.

Electrical overstress (EOS) : devices, circuits, and systems / Steven Voldman.

pages cm

Includes bibliographical references and index.

ISBN 978-1-118-51188-6 (hardback)

1. Semiconductors—Failures. 2. Semiconductors—Protection. 3. Transients (Electricity) 4. Overvoltage. I. Title.

TK7871.852.V648 2013

621.3815—dc23

2013022183

A catalogue record for this book is available from the British Library.

ISBN: 978-1-118-51188-6

To My Mother's Sister

My Aunt

Saundra “Sunny” Braitman

About the Author

Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” He received his B.S. in Engineering Science from University of Buffalo (1979), a first M.S. EE (1981) from Massachusetts Institute of Technology (MIT), a second degree EE Degree (Engineer Degree) from MIT, a MS Engineering Physics (1986), and a Ph.D in electrical engineering (EE; 1991) from University of Vermont under IBM's Resident Study Fellow program.

He was a member of the IBM development for 25 years, working on semiconductor device physics, device design, and reliability e.g., soft error rate (SER), hot electrons, leakage mechanisms, latchup, electrostatic discharge (ESD), and electrical overstress (EOS). Voldman has been involved in latchup technology development for 30 years. He worked on both the technology and product development in Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), BiCMOS, Silicon Germanium (SiGe), RF CMOS, RF SOI, smart power, and image processing technologies. In 2007, Voldman was a member of the Qimonda DRAM development team, working on 70, 58, and 48 nm CMOS technology. In 2008, he initiated a limited liability corporation (LLC), and he worked at headquarters in Hsinchu, Taiwan, for Taiwan Semiconductor Manufacturing Corporation (TSMC) as part of the 45 nm ESD and latchup development team. He was a Senior Principal Engineer working for the Intersil Corporation on ESD and latchup development from 2009 to 2011. Since 2011, he is presently independent under Dr. Steven H. Voldman LLC, providing consulting, teaching, and patent litigation expert witness support. He is presently a consultant for Samsung Electronics in Dongtan, South Korea, working on sub-20 nm technology.

Steve Voldman was chairman of the SEMATECH ESD Working Group from 1995 to 2000. In his SEMATECH Working Group, the effort focused on ESD technology benchmarking, the first transmission line pulse (TLP) standard development team, strategic planning, and the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2012, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He has been a member of the ESD Association Board of Directors, and Education Committee.

Steve Voldman initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Singapore, Taiwan, Malaysia, Philippines, Thailand, South Korea, India, and China.

He teaches short courses and tutorials on ESD, latchup, patenting, and invention in the United States, China, Singapore, Malaysia, Taiwan, Sri Lanka and Israel. He is a recipient of over 245 issued US patents, in the area of ESD and CMOS latchup.

Since 2007, he has served as an expert witness in patent litigation in over six litigation cases, associated with CMOS development, DRAM development, silicon-on-insulator, semiconductor devices, ESD, and latchup.

Steve Voldman has written articles for Scientific American and is author of the first book series on ESD, latchup, and EOS: ESD: Physics and Devices, ESD: Circuits and Devices, ESD : RF Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, and ESD Basics: From Semiconductor Manufacturing to Product Use and this text, Electrical Overstress (EOS): Devices, Circuits and Systems. He is also a contributor to the books Silicon Germanium: Technology, Modeling and Design and Nanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of the book ESD: Circuits and Devices and ESD : RF Technology and Circuit are released as well as others in the near future.

Preface

This text, Electrical Overstress ( EOS ): Devices, Circuits and Systems was initiated based on the need to produce a text that addresses the fundamentals of electrical overstress (EOS) from the manufacturing environment, devices, components and systems. An understanding of the source of EOS, how to identify EOS, and provide EOS robust products are needed in today's electronic industry. As the manufacturing world evolves, semiconductor networks scale, and systems are changing, the needs and requirements for reliability and EOS robust products are changing. A text is required that connects basic EOS phenomena to today's real world environment.

Whereas significant texts are available today to teach experts on electrostatic discharge (ESD) on-chip design, there is a need for a fundamental understanding of EOS. This is necessary for expert, non-expert, non-technical, and layman to understand the problems facing the world today. Today, real world EOS issues surround us; this occurs in manufacturing environment, power sources, machinery, actuators, solenoids, soldering irons, cables, to lightning. When there is switching, poor grounding, ground loops, noise, and transient phenomena, there will be a potential for EOS of devices, components, and printed circuit boards. Hence, there is a need for experts and non-experts to understand what the issues that revolve around us are, and what we do to avoid them.

One of the key problems with this topic is the perception that EOS is difficult to quantify and define. This perception was also true in the early days of ESD development. As a result, there have been no textbooks on EOS at this date, and yet it is understood that a significant percentage of system and product field returns is EOS related.

A second key problem is the belief that it is difficult to distinguish ESD failures from EOS. The reason that this distinction is important is to define the root cause of the device, component, or system failures. As a result, in this text, this will be re-emphasized.

A third key problem is that the techniques and methods to provide both EOS and ESD robust products in the same lecture, tutorial, source, or textbook is never synthesized in one discussion. This is also true that the discussion and training on electromagnetic compatibility (EMC) and ESD are typically taught separately.

This text has multiple goals.

The first goal of the text is to teach the basics and concepts of EOS and relate them to real world processes in semiconductor manufacturing, handling, and assembly.

The second goal of the text is to provide a strong technical base for quantification of EOS, highlighting both mathematical and physical analysis. In this fashion, it is critical to understand the role and relationship of thermal physics.

The third goal of the text is to draw a distinction between EOS and ESD. This will be achieved by focusing on the pulse waveform and time scales. The text will constantly reinforce this distinction through the sources, to the mathematical models.

The fourth goal is to discuss the inter-relationship to other disciplines, such as electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup.

The fifth goal is to expose the reader to EOS testing and standards of both semiconductor chips and systems. In this section, we will again distinguish between the EOS and ESD tests and standards.

The fifth goal is to demonstrate how to protect semiconductor chips and systems from EOS.

The sixth goal is to demonstrate how to protect semiconductor chips and systems from both EOS and ESD events.

The seventh goal is to teach EOS issues in different technology types for digital, analog, and power electronics.

The eighth goal is to highlight electrical design automation (EDA) methods to provide EOS robust products. In this section, we will again draw distinctions of EDA solutions for EOS, ESD, and latchup.

The ninth goal is to discuss an EOS program management for manufacturing environments from measurements to audits, to insure an EOS Protected Area.

The tenth goal is to provide a glimpse into the present and future with new nano-structures and nano-systems that lie ahead. This will provide insight in what will be needed in the future, as well as the magnitude of the EOS concern in coming years.

This text, Electrical Overstress ( EOS ): Devices, Circuits and Systems contains the following:

Chapter 1 introduces the reader to an overview of the language and fundamentals associated with EOS. In Chapter 1, the foundation for a discussion of EOS is established. Chapter 1 opens the dialog of defining EOS and its relationship to other phenomena, such as electrostatic discharge (ESD), electromagnetic interference (EMI), electromagnetic compatibility (EMC), and latchup. EOS is defined as well in terms of electrical over-current, electrical over-power, and other concepts. In our discussion, there is an emphasis on distinguishing EOS from ESD. As a result, I will draw distinctions through the text on difference of failure analysis, time constants, and other means of identification and classification. A plan to define safe operating area (SOA) and its role in EOS is also emphasized.

In Chapter 2, the physical and mathematical basis for understanding EOS is provided. In Chapter 2, the goal is to demonstrate the mathematics and physical models associated with power-to-failure, time constants, and materials. This chapter will provide the tools necessary to understand the equations and physical limits of the electrothermal models derived in the past. A key distinction in this chapter, the ESD time regime from the EOS time regime will be identified to draw attention to the different power-to-failure solutions for these processes. The primary reason for this in-depth discussion is to demonstrate that EOS phenomena can be quantified and understood – which confronts the skeptics that this is not a science which is quantifiable. In the next chapter, we will allow you to recover from the rigor of this chapter, provide practical connection to the real world, and catch your breath.

In Chapter 3, the text's focus returns to a practical discussion on the sources and failure mechanisms associated with EOS. The sources will include machinery, solenoids, actuators, to cables and lightning. EOS failure mechanisms from device component failures, bond pads, bond wires, and packaging are identified. In this chapter, some focus on EOS specific failures from ESD are again be highlighted.

Chapter 4 focuses on EOS failure mechanisms and failure analysis. The chapter highlights failure analysis process, failure analysis techniques, and tools. Failure mechanism examples are shown from the different failure analysis tool results of both EOS and ESD failures.

In Chapter 5, EOS and ESD testing techniques and testing standards are discussed. EOS testing methods discussed include system level tests, such as IEC 61000-4-2, and transient surge standards relevant to EOS (IEC 61000-4-5). The chapter also discusses the ESD tests and standards, such as the human body model (HBM), machine model (MM), charged device model (CDM), transmission line pulse (TLP), very-fast transmission line pulse (VF-TLP), as well as system-like testing. System-like testing begins to transition toward EOS phenomena, (e.g., cable discharge event; CDE) and hence will be part of our discussion on testing.

Chapter 6 discusses EOS in different semiconductor technologies from CMOS, bipolar, LDMOS, to bipolar-CMOS-DMOS (BCD) technologies and the issues that arise in the different application spaces. A focus will be on how the technologies can address power and EOS robustness issues.

The focus in Chapter 7 is EOS design. A key question that arises is, ‘how does EOS design differ from ESD design?’. A second key question is, ‘how do you design for both ESD and EOS in a given chip or system design?’. This chapter includes product definition, specifications, technology identification, to both top-down and bottom-up design methodologies and floor planning. It also shows usage of circuit design to address over-current and over-temperature controls.

In Chapter 8, EOS protection devices are discussed. These include a plethora of elements from snapback devices to voltage triggered devices. EOS protection is achieved using transient voltage suppression (TVS), thyristor surge protection devices (TSPD), metal oxide varistors (MOV), conductive polymers, gas discharge tubes (GDT), fuses, circuit breakers, and other elements. These EOS protection elements are very distinct from those employed for ESD protection.

In Chapter 9, system level problems and solutions are discussed. The focus is on EOS control in the production and manufacturing environment. The chapter addresses preventive actions, controlling the back end process, to product area operations.

In Chapter 10, electronic design automation (EDA) techniques and methods for EOS are discussed. Design rule checking (DRC), layout versus schematic (LVS), to electrical rule checking (ERC) methods are used for both ESD and EOS checking and verification. In this chapter, methods being applied today for EOS environments are shown.

In Chapter 11, an EOS program management process is discussed. The chapter will demonstrate topics on design reviews, checklists, corrective actions, audits, and the design release process to guarantee EOS robust products.

In Chapter 12, EOS in future structures and nano-devices is discussed. The chapter discusses EOS issues in magnetic recording, FinFETs, graphene, carbon nano-tubes, to phase change memory. This concluding chapter takes a look at micro-motors, micro-mirrors, RF MEM switches, and many novel devices. EOS in silicon interposers and through silicon via (TSV) in 2.5-D and 3-D systems is also highlighted.

This introductory text will hopefully open your interest in the field of electrical overstress (EOS), electrostatic discharge (ESD), electromagnetic interference (EMI), and electromagnetic compatibility (EMC) – and teach how it relates to today's world. To establish a stronger knowledge of ESD protection, it is advisable to read the other texts ESD Basics: From Semiconductor Manufacturing to Product Use, ESD: Physics and Devices, ESD: Circuits and Technology, ESD: RF Circuits and Technology, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, and Latchup.

Enjoy the text, and enjoy the subject of EOS – just do not get stressed out over electrical overstress (EOS).

Baruch HaShem

Dr. Steven H. Voldman

IEEE Fellow

Acknowledgments

I would like to thank the years of support from the SEMATECH, the ESD Association, the IEEE, and the JEDEC organizations. I would like to thank the IBM Corporation, Qimonda Corporation, Taiwan Semiconductor Manufacturing Corporation (TSMC), the Intersil Corporation, and the Samsung Corporation. I was fortunate to work in a wide number of technology teams, and with a wide breadth of customers. I was very fortunate to be a member of talented technology and design teams that were both innovative, intelligent, and inventive.

I would like to thank the institutions that allowed me to teach and lecture at conferences, symposiums, industry, and universities; this gave me the motivation to develop the texts. I would like to thank faculty at the following universities: M.I.T., Stanford University, University of Central Florida (UCF), University Illinois Urbana–Champaign (UIUC), University of California Riverside (UCR), University of Buffalo, National Chiao Tung University (NCTU), Tsin Hua University, National Technical University of Science and Technology (NTUST), National University of Singapore (NUS), Nanyang Technical University (NTU), Beijing University, Fudan University, Shanghai Jiao Tung University, Zheijang University, Huazhong University of Science and Technology (HUST), UESTC, Universiti Sains Malaysia (USM), Universiti Putra Malaysia (UPM), Kolej Damansara Utama (KDU), Chulalongkorn University, Mahanakorn University, Kasetsart University, Thammasat University, Korea University, and Mapua Institute of Technology (MIT).

I would like to thank for the years of support and the opportunity to provide lectures, invited talks, and tutorials the Electrical Overstress/Electrostatic Discharge ( EOS/ESD ) Symposium, the International Reliability Physics Symposium ( IRPS ), the Taiwan Electrostatic Discharge Conference ( T-ESDC ), the International Electron Device Meeting ( IEDM ), the International Conference on Solid-State and Integrated Circuit Technology ( ICSICT ), the International Physical and Failure Analysis ( IPFA ), IEEE ASICON, and the IEEE Intelligent Signal Processing And Communication System s ( ISPACS ) Conference.

I would like to thank my many friends for 22 years in the ESD profession – Prof. Ming Dou Ker, Prof. J.J. Liou, Prof. Albert Wang, Prof. Elyse Rosenbaum, Timothy J. Maloney, Charvaka Duvvury, Eugene Worley, Robert Ashton, Yehuda Smooha, Vladislav Vashchenko, Ann Concannon, Albert Wallash, Vessilin Vassilev, Warren Anderson, Marie Denison, Alan Righter, Andrew Olney, Bruce Atwood, Jon Barth, Evan Grund, David Bennett, Tom Meuse, Michael Hopkins, Yoon Huh, Jin Min, Jeffrey Dunnihoo, Keichi Hasegawa, Teruo Suzuki, Han Gu Kim, Kitae Lee, Nathan Peachey, Kathy Muhonen, Augusto Tazzoli, Gaudenzio Menneghesso, Marise BaFleur, Jeremy Smith, Nisha Ram, Swee K. Lau, Tom Diep, Lifang Lou, Stephen Beebe, Michael Chaine, Pee Ya Tan, Theo Smedes, Markus Mergens, Christian Russ, Harold Gossner, Wolfgang Stadler, Ming Hsiang Song, J.C. Tseng, J.H. Lee, Michael Wu, Erin Liao, Stephen Gaul, Jean-Michel Tschann, Tze Wee Chen, Shu Qing Cao, Slavica Malobabic, David Ellis, Blerina Aliaj, Lin Lin, David Swenson, Donn Bellmore, Ed Chase, Doug Smith, W. Greason, Stephen Halperin, Tom Albano, Ted Dangelmayer, Terry Welsher, John Kinnear, and Ron Gibson.

I would like to thank the ESD Association office for their support in the area of publications, standards developments, and conference activities. I would also like to thank the publisher and staff of John Wiley & Sons for including this text as part of the ESD book series.

To my children, Aaron Samuel Voldman, and Rachel Pesha Voldman, good luck to both of you in the future.

To my wife Annie Brown Voldman – thank you for the support of years of work.

And to my parents, Carl and Blossom Voldman.

Baruch HaShem

Dr. Steven H. Voldman

IEEE Fellow