CONTENTS

Cover

Series Page

Title Page

Dedication

Preface

Acknowledgments

Trademarks and Copyrights

About the Companion Website

Chapter 1: Introduction to Microcontrollers and This Book

1.1 Microcontroller Configuration And Structure
1.2 The Arm® Cortex®M4 Microcontroller System
1.3 The TM4C123GH6PM Microcontroller Development Tools and Kits
1.4 Outstanding Features About This Book
1.5 Who This Book is For
1.6 What This Book Covers
1.7 How This Book is Organized and How to Use This Book
1.8 How to Use the Source Code and Sample Projects
1.9 Instructors and Customers Supports

Chapter 2: ARM® Microcontroller Architectures

2.1 Overview and Introduction
2.2 Introduction to ARM® CORTEX®-M4 MCU
2.3 The Memory Architecture
2.4 The Nested Vectored Interrupt Controller (Nvic) Architecture
2.5 The Debug Architecture
2.6 Introduction To Tiva™ C Series Arm® Cortex®-M4 Mcu - Tm4C123Gh6Pm
2.7 Introduction To Tiva™ C Series Launchpad™ Tm4C123Gxl Evaluation Board
2.8 Introduction To Edubase Arm® Trainer
2.9 Chapter Summary
Homework

Chapter 3: ARM® Microcontroller Development Kits

3.1 Overview and Introduction
3.2 The Entire TIVA™ TM4C123G-Based Development System
3.3 Download and Install Development Suite and Specified Firmware
3.4 Introduction to the Integrated Development Environment—Keil® MDK μVersion5
3.5 Embedded Software Development Procedure
3.6 The Keil® ARM®-MDK μVision5 Debugger and Debug Process
3.7 The TivaWare™ for C Series Software Suite
3.8 The TivaWare™ for C Series Utilities and Other Supports
3.9 Program Examples
3.10 Chapter Summary
Homework

Chapter 4: ARM® Microcontroller Software and Instruction Set

4.1 Overview and Introduction
4.2 Introduction to ARM® Cortex®-M4 Software Development Structure
4.3 Introduction to ARM® Cortex®-M4 Assembly Instruction Set
4.4 ARM® Cortex®-M4 Software Development Procedures
4.5 Using C Language to Develop ARM® Cortex®-M4 Microcontroller Applications
4.6 Chapter Summary
Homework

Chapter 5: ARM® Microcontroller Interrupts and Exceptions

5.1 Overview and Introduction
5.2 Exceptions and Interrupts in the ARM® Cortex®-M4 MCU System
5.3 Exceptions and Interrupts in the TM4C123GH6PM Microcontroller System
5.4 Developing GPIO Port Interrupt Projects to Handle GPIO Interrupts
5.5 Comparison Among Four Interrupt Programming Methods
5.6 Chapter Summary
Homework

Chapter 6: ARM® Microcontroller Memory System

6.1 Overview and Introduction
6.2 Memory Architecture in the TM4C123GH6PM MCU System
6.3 Memory Map in TM4C123GH6PM MCU System
6.4 Bit-Band Operations
6.5 Memory Requirements and Memory Properties
6.6 Memory System Programming Methods
6.7 Memory System Programming Projects
6.8 Chapter Summary
Homework

Chapter 7: ARM® Cortex®-M4 Parallel I/O Ports Programming

7.1 Overview and Introduction
7.2 GPIO Module Architecture and GPIO Port Configuration
7.3 GPIO Port Control Registers
7.4 On-Board Keypad Interface Programming Project
7.5 Analog-to-Digital Converter Programming Project
7.6 PWM-Controlled DC and Step Motors Programming Project
7.7 THE PWM API Functions in the Tivaware™ Peripheral Driver Library
7.8 Chapter Summary
Homework

Chapter 8: ARM® Cortex®-M4 Serial I/O Ports Programming

8.1 Overview and Introduction
8.2 GPIO Module Architecture and GPIO Port Configuration
8.3 Synchronous Serial Interface (SSI)
8.4 Inter-Integrated Circuit (I2C) Interface
8.5 Universal Asynchronous Receivers/Transmitters (UARTs)
8.6 Chapter Summary
Homework

Chapter 9: ARM® Cortex®-M4 Timer and USB Programming

9.1 Overview and Introduction
9.2 General-Purpose Timers
9.3 Watchdog Timers
9.4 Universal Serial Bus (USB) Controller
9.5 Chapter Summary
Homework

Chapter 10: ARM® Cortex®-M4 Other Peripherals Programming

10.1 Overview and Introduction
10.2 The Controller Area Network (CAN)
10.3 The Quadrature Encoder Interface (QEI)
10.4 The Continuous and Discrete PID Closed-Loop Control System
10.5 The Fuzzy Logic Closed-Loop Control System
10.6 The Analog Comparators
10.7 Chapter Summary
Homework

Chapter 11: ARM® Floating Point Unit (FPU)

11.1 Overview and Introduction
11.2 Three Types of the Floating-Point Data
11.3 The FPU in the Cortex®-M4 MCU
11.4 Implementing the Floating-Point Unit
11.5 Chapter Summary
Homework

Chapter 12: ARM® Memory Protection Unit (MPU)

12.1 Overview and Introduction
12.2 Implementation of the MPU
12.3 Initialization and Configuration of the MPU
12.4 Building a Practical Example MPU Project
12.5 The API Functions Provided by the Tivaware™ Peripheral Driver Library
12.6 Chapter Summary
Homework

Index

About the Author

End User License Agreement

List of Tables

Table 2.1

Table 2.2

Table 2.3

Table 2.4

Table 2.5

Table 2.6

Table 2.7

Table 2.8

Table 2.9

Table 2.10

Table 2.11

Table 2.12

Table 2.13

Table 2.14

Table 2.15

Table 2.16

Table 2.17

Table 2.18

Table 2.19

Table 2.20

Table 2.21

Table 2.22

Table 2.23

Table 3.1

Table 3.2

Table 3.3

Table 4.1

Table 4.2

Table 4.3

Table 4.4

Table 4.5

Table 4.6

Table 4.7

Table 4.8

Table 4.9

Table 4.10

Table 4.11

Table 4.12

Table 4.13

Table 4.14

Table 4.15

Table 4.16

Table 4.17

Table 4.18

Table 4.19

Table 4.20

Table 4.21

Table 4.22

Table 4.23

Table 4.24

Table 4.25

Table 4.26

Table 4.27

Table 4.28

Table 5.1

Table 5.2

Table 5.3

Table 5.4

Table 5.5

Table 5.6

Table 5.7

Table 5.8

Table 5.9

Table 5.10

Table 5.11

Table 5.12

Table 5.13

Table 5.14

Table 5.15

Table 5.16

Table 5.17

Table 5.18

Table 5.19

Table 5.20

Table 5.21

Table 5.22

Table 5.23

Table 6.1

Table 6.2

Table 6.3

Table 6.4

Table 6.5

Table 6.6

Table 6.7

Table 6.8

Table 6.9

Table 6.10

Table 6.11

Table 6.12

Table 6.13

Table 6.14

Table 6.15

Table 6.16

Table 6.17

Table 6.18

Table 6.19

Table 6.20

Table 7.1

Table 7.2

Table 7.3

Table 7.4

Table 7.5

Table 7.6

Table 7.7

Table 7.8

Table 7.9

Table 7.10

Table 7.11

Table 7.12

Table 7.13

Table 7.14

Table 7.15

Table 7.16

Table 7.17

Table 7.18

Table 7.19

Table 7.20

Table 7.21

Table 7.22

Table 7.23

Table 7.24

Table 7.25

Table 7.26

Table 7.27

Table 7.28

Table 7.29

Table 7.30

Table 7.31

Table 7.32

Table 7.33

Table 7.34

Table 7.35

Table 7.36

Table 7.37

Table 7.38

Table 8.1

Table 8.2

Table 8.3

Table 8.4

Table 8.5

Table 8.6

Table 8.7

Table 8.8

Table 8.9

Table 8.10

Table 8.11

Table 8.12

Table 8.13

Table 8.14

Table 8.15

Table 8.16

Table 8.17

Table 8.18

Table 8.19

Table 8.20

Table 8.21

Table 8.22

Table 8.23

Table 8.24

Table 8.25

Table 8.26

Table 8.27

Table 8.28

Table 8.29

Table 8.30

Table 8.31

Table 8.32

Table 8.33

Table 8.34

Table 8.35

Table 8.36

Table 8.37

Table 8.38

Table 8.39

Table 8.40

Table 9.1

Table 9.2

Table 9.3

Table 9.4

Table 9.5

Table 9.6

Table 9.7

Table 9.8

Table 9.9

Table 9.10

Table 9.11

Table 9.12

Table 9.13

Table 9.14

Table 9.15

Table 9.16

Table 9.17

Table 9.18

Table 9.19

Table 9.20a

Table 9.20b

Table 9.20c

Table 9.20d

Table 9.21

Table 9.22

Table 9.23

Table 9.24

Table 9.25

Table 9.26

Table 9.27

Table 9.28

Table 9.29

Table 10.1

Table 10.2

Table 10.3

Table 10.4

Table 10.5

Table 10.6

Table 10.7

Table 10.8

Table 10.9

Table 10.10

Table 10.11

Table 10.12

Table 10.13

Table 10.14

Table 10.15

Table 10.16

Table 10.17

Table 10.18

Table 10.19

Table 10.20

Table 10.21

Table 10.22

Table 10.23

Table 10.24

Table 10.25

Table 10.26

Table 10.27

Table 10.28

Table 11.1

Table 11.2

Table 11.3

Table 11.4

Table 11.5

Table 12.1

Table 12.2

Table 12.3

Table 12.4

Table 12.5

Table 12.6

Table 12.7

Table I

Table II

List of Illustrations

Figure 1.1

Figure 1.2

Figure 1.3

Figure 2.1

Figure 2.2

Figure 2.3

Figure 2.4

Figure 2.5

Figure 2.6

Figure 2.7

Figure 2.8

Figure 2.9

Figure 2.10

Figure 2.11

Figure 2.12

Figure 2.13

Figure 2.14

Figure 2.15

Figure 2.16

Figure 2.17

Figure 2.18

Figure 2.19

Figure 2.20

Figure 2.21

Figure 2.22

Figure 3.1

Figure 3.2

Figure 3.3

Figure 3.4

Figure 3.5

Figure 3.6

Figure 3.7

Figure 3.8

Figure 3.9

Figure 3.10

Figure 3.11

Figure 3.12

Figure 3.13

Figure 3.14

Figure 3.15

Figure 3.16

Figure 3.17

Figure 3.18

Figure 3.19

Figure 3.20

Figure 3.21

Figure 3.22

Figure 3.23

Figure 3.24

Figure 3.25

Figure 3.26

Figure 3.27

Figure 3.28

Figure 3.29

Figure 3.30

Figure 3.31

Figure 3.32

Figure 3.33

Figure 3.34

Figure 3.35

Figure 3.36

Figure 3.37

Figure 3.38

Figure 3.39

Figure 3.40

Figure 3.41

Figure 3.42

Figure 3.43

Figure 3.44

Figure 3.45

Figure 3.46

Figure 3.47

Figure 3.48

Figure 3.49

Figure 3.50

Figure 3.51

Figure 3.52

Figure 3.53

Figurer 3.54

Figure 3.55

Figure 3.56

Figure 4.1

Figure 4.2

Figure 4.3

Figure 4.4

Figure 4.5

Figure 4.6

Figure 4.7

Figure 4.8

Figure 4.9

Figure 4.10

Figure 4.11

Figure 4.12

Figure 4.13

Figure 4.14

Figure 4.15

Figure 4.16

Figure 4.17

Figure 4.18

Figure 4.19

Figure 4.20

Figure 4.21

Figure 4.22

Figure 4.23

Figure 4.24

Figure 4.25

Figure 4.26

Figure 4.27

Figure 4.28

Figure 4.29

Figure 4.30

Figure 4.31

Figure 4.32

Figure 4.33

Figure 4.34

Figure 4.35

Figure 4.36

Figure 4.37

Figure 4.38

Figure 4.39

Figure 4.40

Figure 4.41

Figure 5.1

Figure 5.2

Figure 5.3

Figure 5.4

Figure 5.5

Figure 5.6

Figure 5.7

Figure 5.8

Figure 5.9

Figure 5.10

Figure 5.11

Figure 5.12

Figure 5.13

Figure 5.14

Figure 5.15

Figure 5.16

Figure 5.17

Figure 5.18

Figure 5.19

Figure 5.20

Figure 5.21

Figure 5.22

Figure 5.23

Figure 5.24

Figure 5.25

Figure 6.1

Figure 6.2

Figure 6.3

Figure 6.4

Figure 6.5

Figure 6.6

Figure 6.7

Figure 6.8

Figure 6.9

Figure 6.10

Figure 6.11

Figure 6.12

Figure 6.13

Figure 6.14

Figure 6.15

Figure 6.16

Figure 6.17

Figure 6.18

Figure 6.19

Figure 6.20

Figure 6.21

Figure 6.22

Figure 6.23

Figure 6.24

Figure 6.25

Figure 6.26

Figure 6.27

Figure 6.28

Figure 6.29

Figure 6.30

Figure 6.31

Figure 6.32

Figure 6.33

Figure 6.34

Figure 6.35

Figure 6.36

Figure 6.37

Figure 6.38

Figure 6.39

Figure 6.40

Figure 6.41

Figure 6.42

Figure 7.1

Figure 7.2

Figure 7.3

Figure 7.4

Figure 7.5

Figure 7.6

Figure 7.7

Figure 7.8

Figure 7.9

Figure 7.10

Figure 7.11

Figure 7.12

Figure 7.13

Figure 7.14

Figure 7.15

Figure 7.16

Figure 7.17

Figure 7.18

Figure 7.19

Figure 7.20

Figure 7.21

Figure 7.22

Figure 7.23

Figure 7.24

Figure 7.25

Figure 7.26

Figure 7.27

Figure 7.28

Figure 7.29

Figure 7.30

Figure 7.31

Figure 7.32

Figure 7.33

Figure 7.34

Figure 7.35

Figure 7.36

Figure 7.37

Figure 7.38

Figure 7.39

Figure 7.40

Figure 7.41

Figure 7.42

Figure 7.43

Figure 7.44

Figure 7.45

Figure 7.46

Figure 7.47

Figure 7.48

Figure 7.49

Figure 8.1

Figure 8.2

Figure 8.3

Figure 8.4

Figure 8.5

Figure 8.6

Figure 8.7

Figure 8.8

Figure 8.9

Figure 8.10

Figure 8.11

Figure 8.12

Figure 8.13

Figure 8.14

Figure 8.15

Figure 8.16

Figure 8.17

Figure 8.18

Figure 8.19

Figure 8.20

Figure 8.21

Figure 8.22

Figure 8.23

Figure 8.24

Figure 8.25

Figure 8.26

Figure 8.27

Figure 8.28

Figure 8.29

Figure 8.30

Figure 8.31

Figure 8.32

Figure 8.33

Figure 8.34

Figure 8.35

Figure 8.36

Figure 8.37

Figure 8.38

Figure 8.39

Figure 8.40

Figure 8.41

Figure 8.42

Figure 8.43

Figure 8.44

Figure 8.45

Figure 8.46

Figure 8.47

Figure 8.48

Figure 8.49

Figure 8.50

Figure 8.51

Figure 8.52

Figure 8.53

Figure 8.54

Figure 8.55

Figure 8.56

Figure 8.57

Figure 8.58

Figure 8.59

Figure 8.60

Figure 8.61

Figure 8.62

Figure 8.63

Figure 8.64

Figure 8.65

Figure 8.66

Figure 8.67

Figure 8.68

Figure 8.69

Figure 8.70

Figure 8.71

Figure 8.72

Figure 8.73

Figure 8.74

Figure 8.75

Figure 8.76

Figure 9.1

Figure 9.2

Figure 9.3

Figure 9.4

Figure 9.5

Figure 9.6

Figure 9.7

Figure 9.8

Figure 9.9

Figure 9.10

Figure 9.11

Figure 9.12

Figure 9.13

Figure 9.14

Figure 9.15

Figure 9.16

Figure 9.17

Figure 9.18

Figure 9.19

Figure 9.20

Figure 9.21

Figure 9.22

Figure 9.23

Figure 9.24

Figure 9.25

Figure 9.26

Figure 9.27

Figure 9.28

Figure 9.29

Figure 9.30

Figure 9.31

Figure 9.32

Figure 9.33

Figure 10.1

Figure 10.2

Figure 10.3

Figure 10.4

Figure 10.5

Figure 10.6

Figure 10.7

Figure 10.8

Figure 10.9

Figure 10.10

Figure 10.11

Figure 10.12

Figure 10.13

Figure 10.14

Figure 10.15

Figure 10.16

Figure 10.17

Figure 10.18

Figure 10.19

Figure 10.20

Figure 10.21

Figure 10.22

Figure 10.23

Figure 10.24

Figure 10.25

Figure 10.26

Figure 10.27

Figure 10.28

Figure 10.29

Figure 10.30

Figure 10.31

Figure 10.32

Figure 10.33

Figure 10.34

Figure 10.35

Figure 10.36

Figure 10.37

Figure 10.38

Figure 10.39

Figure 10.40

Figure 10.41

Figure 10.42

Figure 10.43

Figure 10.44

Figure 10.45

Figure 10.46

Figure 10.47

Figure 10.48

Figure 10.49

Figure 10.50

Figure 10.51

Figure 10.52

Figure 10.53

Figure 10.54

Figure 10.55

Figure 10.56

Figure 10.57

Figure 10.58

Figure 10.59

Figure 10.60

Figure 10.61

Figure 10.62

Figure 10.63

Figure 10.64

Figure 10.65

Figure 10.66

Figure 10.67

Figure 10.68

Figure 11.1

Figure 11.2

Figure 11.3

Figure 11.4

Figure 11.5

Figure 11.6

Figure 11.7

Figure 11.8

Figure 11.9

Figure 11.10

Figure 11.11

Figure 11.12

Figure 12.1

Figure 12.2

Figure 12.3

Figure 12.4

Figure 12.5

Figure 12.6

Published simultaneously in Canada

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Library of Congress Cataloging-in-Publication Data is available.

ISBN: 978-1-119-05237-1

Preface

The ARM® Cortex®-M4 MCU is one of the most popular and updated microcontrollers widely implemented in education, industrial, and manufacturing fields in recent years. Because of their relatively simple structure and powerful functions, the ARM® Cortex®-M4 MCU systems have been applied in more and more applications in our real world, including automatic controls, intelligent controls, industrial controls, and academic implementations.

The advantages of using an ARM® Cortex®-M4 microcontroller include but are not limited to the following:

The ARM® Cortex®-M4 MCU is a 32-bit microcontroller, and it can work independently as a single controller to provide real-time and multifunction controls to effectively and easily control most real objectives in our world.
The internal bus system used in Cortex®-M4 MCU is 32-bit, and it is based on the so-called Advanced Microcontroller Bus Architecture (AMBA) standard. The AMBA standard provides efficient operations and low power cost on the hardware.
The main bus interface between the MCU and external components is the Advanced High-performance Bus (AHB), which provide interfaces for memory and system bus, as well as peripheral devices.
A Nested Vectored Interrupt Controller (NVIC) is used to provide all supports and managements to the interrupt responses and processing to all components in the system.
The Cortex®-M4 MCU also provides standard and extensive debug features and helps to enable users to easily check and trace their program with breakpoints and steps.
The TM4C123GXL EVB provides fundamental and basic peripherals and interfaces to enable users to conveniently communicate to other parallel or serial peripherals via GPIO Ports to perform specific control tasks and functions.
The EduBASE ARM® Trainer provides the most popular I/O devices, such as 4-LED, a 4-bit DIP switch, four 7-segment LEDs, a 4×4 keypad working as an input keyboard, a 16×2 LCD connected to the LCD Controller HD44780 to work as an output displaying device, two H-Bridge motor drivers, three analog input sensors, a CAN protocol and other peripheral interfaces. All of these I/O devices and interfaces provide great flexibility to enable users to design and build advanced and professional control units applied in our real world.
The integrated development environment Keil® ARM-MDK μVersion®5 provides an integrated development environment to enable users to easily create, compile, build, and run professional application projects to control and coordinate the entire control system to perform a desired task in short period of time.

The author of this book tries to provide a complete package to cover all components and materials related to ARM® Cortex®-M4 microcontroller systems, including hardware and software as well as practical application notes with real examples. All example projects in the book have been compiled, built, and tested. To help students to master the main techniques and ideas, five appendices are provided to facilitate the students to overcome some possible learning curves.

Any questions or comments regarding this book are welcome.

Charlotte, North Carolina

Ying Bai

Copyright Permissions

All copyright permitted Figures and Tables used in this book are listed below based on the different venders and companies.

Table I lists the copyright permitted Figures and Tables originated by the Texas Instruments Incorporated and used in this book. All those Figures and Tables have been permitted to be re-printed in this book under the copyright permissions of the Texas Instruments Incorporated.

Table I Copyright Permitted Figures and Tables by Texas Instruments Incorporated.

Chapter	Figures and Tables	Page
Chapter 2	Figure 2.14: Block diagram of TM4C123GH6PM MCU. Figure 2.17: Function block diagram of Analog/Digital GPIO control. Figure 2.20: The TM4C123GXL evaluation board. Figure 2.21: The functional block diagram of the LaunchPad board. Table 2.3: Exception and interrupt types and priority numbers. Table 2.8: GPIO Pins with special considerations.	39 48 73 76 36 58
Chapter 4	Figure 4.34: An example of using mask byte to do data reading and writing.	230
Chapter 5	Figure 5.6: An example of the NVIC Priority Level Register PRI0.	276
Chapter 6	Figure 6.3: Bit field and function on BOOTCFG Register. Figure 6.4: Bit field and function on FMA Register. Figure 6.5: Bit field and function on the FMC Register. Figure 6.6: Bit field and function on the FMC2 Register. Figure 6.7: Bit field and function on FCRIS Register. Figure 6.8: Bit field and function on FCIM Register. Figure 6.9: Bit field and function on FCMISC Register. Figure 6.11: The functional block diagram of the EEPROM. Figure 6.12: The bit field values and related functions in the EEDONE register. Figure 6.13: The bit field values and related functions in the EEPROT register.	339 341 342 343 344 346 347 355 358 360
Chapter 7	Figure 7.12: The bit fields for the ADCSSMUX0 register. Figure 7.13: The bit fields for the ADCSSMUX1, 2 registers. Figure 7.14: The bit fields for the ADCSSMUX3 register. Figure 7.15: The bit fields for the ADCSSCTL0 register. Figure 7.16: The bit fields for the ADCSSCTL1, 2 registers. Figure 7.17: The bit fields for the ADCSSCTL3 register. Figure 7.32: PWM Count-Down and Count Up/Down modes. Figure 7.33: An example of using the count-up/down mode to generate PWM outputs. Figure 7.34: The output PWM signals generated by Dead-Band generator. Figure 7.35: The detailed block diagram for the PWM Generator block. Figure 7.36: Bit fields in the PWM generator control register. Figure 7.37: Bit fields in the PWM generator A register. Figure 7.41: Architecture and functional block diagram of PWM module. Figure 7.42: Bit fields in the Run-Mode Clock Configuration (RCC) register.	452 453 454 455 456 458 488 489 490 491 492 494 503 504
Chapter 8	Figure 8.4: Functional block diagram of the SSI module. Figure 8.5: Operational timing sequence of the TI synchronous serial frame. Figure 8.6: The operational sequence for Freescale SPI frame (SPO = SPH = 0). Figure 8.7: The operational sequence for Freescale SPI frame (SPO = 0, SPH = 1). Figure 8.8: The operational sequence for MACROWIRE frame. Figure 8.11: The bit field and functions of the SSICR0 Register. Figure 8.42: The I2C bus configuration and status. Figure 8.43: The definition of START and STOP conditions. Figure 8.44: The functional block diagram of each I2C module. Figure 8.45: The I2C data transfer format and frame. Figure 8.46: The operational sequence of the master working in the transmit mode. Figure 8.47: The operational sequence of the master working in the receive mode. Figure 8.48: The operational sequence of the I2C module working in the slave mode. Figure 8.62: The functional block diagram for one UART module. Figure 8.65: Bit configurations of the UARTCTL register.	556 558 559 559 560 563 612 612 613 614 615 617 618 644 652
Chapter 9	Figure 9.1: The architecture and block diagram of one GPTM block. Figure 9.3: An example of using a count-down timer to detect input edge events. Figure 9.4: An example of using the count-down mode timer to detect the edge time. Figure 9.5: An example of using Timer A to generate a PWM signal. Figure 9.20: The functional block diagram of the watchdog modules. Figure 9.27: Functional block diagram of the USB module.	693 700 701 703 734 760
Chapter 10	Figure 10.2: A typical standard CAN frame format. Figure 10.3: Functional block diagram of the CAN modules. Figure 10.5: A normal CAN bit time configuration. Figure 10.25: Functional block diagram of the QEI Modules. Figure 10.26: The inversion and swapping logic circuit. Figure 10.63: Architecture and functional block diagram of the Analog Comparator modules.	807 809 820 851 852 900

Table II lists the copyright permitted Figures and Tables originated by the ARM Limited and used in this book. All those Figures and Tables have been reproduced with permission from ARM Limited. Copyright © ARM Limited.

Table II Copyright Permitted Figures and Tables by ARM Limited.

Chapter	Figures and Tables	Page
Chapter 3	Figure 3.4: The components included in the MDK Core. Figure 3.5: Components in the Software Packs. Figure 3.9: The opened Keil® MDK-ARM μVersion® 5.1 suite. Figure 3.11: The opened Hello World project. Figure 3.12: The opened source file hello.c. Figure 3.13: Rebuild the hello project. Figure 3.14: The building result of the hello project. Figure 3.15: The debugging result of the hello world project. Figure 3.16: The opened MDK-ARM IDE. Figure 3.17: The opened Device Database wizard. Figure 3.18: The detailed information for the device TM4C123GH6PM. Figure 3.19: The License Management wizard. Figure 3.20: An example of the Configuration submenu. Figure 3.22: The Select Device for Target wizard. Figure 3.23: The Manage Run-Time Environment wizard. Figure 3.24: The selected components in the Manage Run-Time Environment wizard. Figure 3.25: The new project wizard. Figure 3.26: The Add New Item to Group wizard. Figure 3.28: The finished codes for the source file MyProject.c. Figure 3.29: Add a header file MyProject.h into the project. Figure 3.31: The finished header file MyProject.h. Figure 3.32: The project building process. Figure 3.33: The finished debugger checking wizard. Figure 3.34: The download process for our project. Figure 3.35: The debug process for our project. Figure 3.36: The Components, Environment, Books wizard. Figure 3.37: The Manage Run-Time Environment wizard for our sample project. Figure 3.38: Functions provided by the Options for Target Project wizard. Figure 3.39: The Target option for the sample project MyProject. Figure 3.40: The Output option for the sample project MyProject. Figure 3.41: The Listing option for the sample project MyProject. Figure 3.42: The Debug option for the sample project MyProject. Figure 3.43: The Utilities option for the sample project MyProject. Figure 3.44: The opened Settings wizard. Figure 3.45: An example of using System Viewer for TIMER0 device. Figure 3.46: The Nested Vectored Interrupt Controller configuration dialog. Figure 3.50: A debug example for our sample project MyProject. Figure 3.51: The optimization wizard for our sample project. Figure 3.52: An example of using the code optimization under the Target tab.	87 88 92 93 94 95 95 96 97 98 99 99 100 103 103 104 105 106 108 108 109 110 111 111 112 114 114 116 116 117 117 119 119 120 123 125 134 139 141
Chapter 4	Figure 4.38: The finished Options wizard.	236
Chapter 6	Figure 6.26: The running result of the project DRAFlash. Figure 6.27: The 1-KB erased flash memory block (0x1000~0x13FF). Figure 6.32: The running result of the DRAFlashInt project. Figure 6.34: The running result of the project DRAFlashBuffer. Figure 6.38: The 18 read-out data stored in the data array prData[]. Figure 6.42: The read back data stored in the prData[] array.	387 388 397 400 414 420
Chapter 8	Figure 8.74: Running result of the project DRAUART. Figure 8.75: Running result of the project Lab8_5. Figure 8.76: Running result of the project Lab8_6.	664 685 689
Chapter 11	Figure 11.6: The FPU is automatically used in MDK-ARM μVersion 5 IDE. Figure 11.11: The running result of the project DRAFPU.	939 945

Table III list the copyright permitted Figures and Tables originated by the MathWorks, Inc. and used in this book. All those Figures and Tables have been permitted to be re-printed in this book under the copyright permissions of the MathWorks, Inc.

Chapter	Figures and Tables	Page
Chapter 10	Figure 10.38: The MATLAB Script file getMData.m. Figure 10.39: Load the data array mdata.dat into the MATLAB Workspace. Figure 10.40: The opened Identification Toolbox and Import data wizard. Figure 10.41: The modified data array mdatad in the identification Toolbox. Figure 10.42: The opened Process Models wizard. Figure 10.43: The identified model responses and analysis. Figure 10.44: Commands used to set transfer function of the DC motor and start PID tuner. Figure 10.45: The opened PID Tuner and the tuning result. Figure 10.46: The opened SIMULINK window. Figure 10.47: The finished SIMULINK bock connections. Figure 10.48: The simulated step response result. Figure 10.51: The step response of the actual closed-loop motor control system. Figure 10.55: Graphic representation of the control rules. Figure 10.56: The fuzzy output surface or envelope. Figure 10.62: The step response of the fuzzy logic control system.	875 876 876 877 878 879 880 880 881 882 883 886 890 890 898
Chapter 11	Figure 11.12: The plotting result for the data array gSData[].	945

George W. Arnold	Vladimir Lumelsky	Linda Shafer
Dmitry Goldgof	Pui-In Mak	Zidong Wang
Ekram Hossain	Jeffrey Nanzer	MengChu Zhou
Mary Lanzerotti	Ray Perez	George Zobrist