reading

Cover
Title Page
Title Page
Copyright
Volume 1
Preface
1. Introduction
2. References
Part I: Silicon Carbide (SiC)
1. 1 Dislocation Formation During Physical Vapor Transport Growth of 4H‐SiC Crystals
  1. 1.1 Introduction
  2. 1.2 Formation of Basal Plane Dislocations During PVT Growth of 4H‐SiC Crystals
  3. 1.3 Dislocation Formation During Initial Stage of PVT Growth of 4H‐SiC Crystals
  4. 1.4 Conclusions
  5. References
2. 2 Industrial Perspectives of SiC Bulk Growth
  1. 2.1 Introduction
  2. 2.2 SiC Substrates for GaN LEDs
  3. 2.3 SiC Substrates for Power SiC Devices
  4. 2.4 SiC Substrates for High‐Frequency Devices
  5. 2.5 Cost Considerations for Commercial Production of SiC
  6. 2.6 Raw Materials
  7. 2.7 Reactor Hot Zone
  8. 2.8 System Equipment
  9. 2.9 Yield
  10. 2.10 Turning Boules into Wafers
  11. 2.11 Crystal Grind
  12. 2.12 Wafer Slicing
  13. 2.13 Wafer Polish
  14. 2.14 Summary
  15. Acknowledgments
  16. References
3. 3 Homoepitaxial Growth of 4H‐SiC on Vicinal Substrates
  1. 3.1 Introduction
  2. 3.2 Fundamentals of 4H‐SiC Homoepitaxy for Power Electronic Devices
  3. 3.3 Extended Defects in Homoepitaxial Layers
  4. 3.4 Point Defects and Carrier Lifetime in Epilayers
  5. 3.5 Conclusion
  6. Acknowledgments
  7. References
4. 4 Industrial Perspective of SiC Epitaxy
  1. 4.1 Introduction
  2. 4.2 Background
  3. 4.3 The Basics of SiC Epitaxy
  4. 4.4 SiC Epi Historical Origins
  5. 4.5 Planetary Multi‐wafer Epitaxial Reactor Design Considerations
  6. 4.6 Latest High‐Throughput Epitaxial Reactor Status
  7. 4.7 Benefits and Challenges for Increasing Growth Rate in all Reactors
  8. 4.8 Increasing Wafer Diameters, Device Processing Considerations, and Projections
  9. 4.9 Summary
  10. Acknowledgment
  11. References
5. 5 Status of 3C‐SiC Growth and Device Technology
  1. 5.1 Introduction, Motivation, Short Review on 3C‐SiC
  2. 5.2 Nucleation and Epitaxial Growth of 3C‐SC on Si
  3. 5.3 Bulk Growth of 3C‐SiC
  4. 5.4 Processing and Testing of 3C‐SiC Based Power Electronic Devices
  5. 5.5 Summary
  6. Acknowledgements
  7. References
6. 6 Intrinsic and Extrinsic Electrically Active Point Defects in SiC
  1. 6.1 Characterization of Electrically Active Defects
  2. 6.2 Intrinsic Electrically Active Defects in SiC
  3. 6.3 Transition Metal and Other Impurity Levels in SiC
  4. 6.4 Summary
  5. References
7. 7 Dislocations in 4H‐SiC Substrates and Epilayers
  1. 7.1 Introduction
  2. 7.2 Dislocations in Bulk 4H‐SiC
  3. 7.3 Dislocations in Homoepitaxial 4H‐SiC
  4. 7.4 Summary
  5. Acknowledgments
  6. References
8. 8 Novel Theoretical Approaches for Understanding and Predicting Dislocation Evolution and Propagation
  1. 8.1 Introduction
  2. 8.2 General Modeling and Simulation Approaches
  3. 8.3 Continuum Dislocation Modeling Approaches
  4. 8.4 Example 1: Comparison of the Alexander–Haasen and the Groma Model
  5. 8.5 Example 2: Dislocation Flow Between Veins
  6. 8.6 Summary and Conclusion
  7. References
9. 9 Gate Dielectrics for 4H‐SiC Power Switches: Understanding the Structure and Effects of Electrically Active Point Defects at the 4H‐SiC/SiO₂ Interface
  1. 9.1 Introduction
  2. 9.2 Electrical Impact of Traps on MOSFET Characteristics
  3. 9.3 Microscopic Nature of Electrically Active Traps Near the Interface
  4. 9.4 Conclusions and Outlook
  5. References
10. 10 Epitaxial Graphene on Silicon Carbide as a Tailorable Metal–Semiconductor Interface
  1. 10.1 Introduction
  2. 10.2 Epitaxial Graphene as a Metal
  3. 10.3 Fabrication and Structuring of Epitaxial Graphene
  4. 10.4 Epitaxial Graphene as Tailorable Metal/Semiconductor Contact
  5. 10.5 Monolithic Epitaxial Graphene Electronic Devices and Circuits
  6. 10.6 Novel Experiments on Light–Matter Interaction Enabled by Epitaxial Graphene
  7. 10.7 Conclusion
  8. Acknowledgments
  9. References
11. 11 Device Processing Chain and Processing SiC in a Foundry Environment
  1. 11.1 Introduction
  2. 11.2 DMOSFET Structure
  3. 11.3 Process Integration of SiC MOSFETs
  4. 11.4 Commercial Foundries for Si and SiC Devices
  5. 11.5 Dedicated Foundries vs. Commercial Foundries
  6. References
12. 12 Unipolar Device in SiC: Diodes and MOSFETs
  1. 12.1 Introduction
  2. 12.2 Unipolar Diodes – 4H‐SiC JBS Diodes
  3. 12.3 Unipolar Switches: Power MOSFETs
  4. 12.4 Summary
  5. References
13. Volume 2
14. 13 Ultra‐High‐Voltage SiC Power Device
  1. 13.1 Introduction
  2. 13.2 Ultra‐high‐voltage SiC PiN diode and SiC‐IGBT
  3. 13.3 Reverse Characteristics of SiC Bipolar Device
  4. 13.4 Carrier Lifetime Dependence on the Characteristics of Bipolar Device
  5. 13.5 Design and Device Performance of Bipolar Device
  6. 13.6 Current Status of SiC Bipolar Device
  7. References
15. 14 SiC Reliability Aspects
  1. 14.1 Ruggedness and Overload Events
  2. 14.2 Cosmic‐Ray Stability
  3. 14.3 Thermomechanical Reliability
  4. 14.4 New Power‐module Technologies with Sufficient Reliability
  5. Acknowledgments
  6. References
16. 15 Industrial Systems Using SiC Power Devices
  1. 15.1 Introduction
  2. 15.2 DC/DC Converters
  3. 15.3 Solid‐State Transformer (SST)
  4. 15.4 Wireless Charging
  5. 15.5 Inductive Heating
  6. 15.6 Photovoltaic
  7. 15.7 DC Grids
  8. 15.8 High‐Voltage DC (HVDC)
  9. 15.9 Drives
  10. 15.10 Conclusions
  11. Acknowledgements
  12. References
17. 16 Special Focus on HEV and EV Applications: Activities of Automotive Industries Applying SiC Devices for Automotive Applications
  1. 16.1 Background (PDPlus LLC)
  2. 16.2 The Challenge of SiC Power Devices Introductions on Prototype HEVs and FCVs (TOYOTA MOTOR CORPORATION)
  3. 16.3 Introduction of Boost Converter Using SiC Semiconductor for New FCV Drive (HONDA MOTOR CO., LTD.)
  4. 16.4 Development of Module Technologies to Bring Out SiC Power Device Performances (TOYOTA MOTOR CORPORATION)
  5. 16.5 SiC‐MOSFET Switching Characteristics and Gate Driver Circuits for Automotive Application (NISSAN MOTOR CO., LTD.)
  6. 16.6 R&D of SiC Power Devices for Automotive Applications (DENSO CORPORATION)
  7. Acknowledgments
  8. References
18. 17 Point Defects in Silicon Carbide for Quantum Technology
  1. 17.1 Introduction
  2. 17.2 Silicon Carbide: Polytypes and Types of Relevant Point Defects
  3. 17.3 Point Defect Single Photon Sources and Quantum Bits
  4. 17.4 Conclusion
  5. Acknowledgments
  6. References
Part II: Gallium Nitride (GaN), Diamond, and Ga₂O₃
1. 18 Ammonothermal and HVPE Bulk Growth of GaN
  1. 18.1 Introduction
  2. 18.2 HVPE Method – History and State of the Art
  3. 18.3 Ammonothermal Method – History and State of the Art
  4. 18.4 HVPE‐GaN‐on‐Ammono‐GaN – State of the Art
  5. 18.5 Summary
  6. Acknowledgments
  7. References
2. 19 GaN on Si: Epitaxy and Devices
  1. 19.1 Introduction
  2. 19.2 GaN Epitaxy on Si Substrate
  3. 19.3 Lateral GaN Devices on Si Substrate
  4. 19.4 Application of GaN HFET
  5. 19.5 Integration of Lateral GaN Devices
  6. 19.6 Summary
  7. Acknowledgments
  8. References
3. 20 Growth of Single Crystal Diamond Wafers for Future Device Applications
  1. 20.1 Introduction
  2. 20.2 High‐Pressure High‐Temperature (HPHT) Synthesis
  3. 20.3 Chemical Vapor Deposition (CVD)
  4. 20.4 State of the Art and Outlook
  5. Acknowledgments
  6. References
  7. Note
4. 21 Diamond Wafer Technology, Epitaxial Growth, and Device Processing
  1. 21.1 Diamond Epitaxial Growth and Wafers
  2. 21.2 n‐Type Doping and Processing
  3. 21.3 p‐Type Doping and Processing
  4. 21.4 Devices
  5. References
5. 22 Gallium Oxide: Material Properties and Devices
  1. 22.1 Introduction
  2. 22.2 Physical Properties of Ga₂O₃
  3. 22.3 Melt Bulk Growth
  4. 22.4 Epitaxial Growth
  5. 22.5 Vertical Diodes
  6. 22.6 Lateral FETs
  7. 22.7 Vertical FETs
  8. 22.8 Summary
  9. References
Index
End User License Agreement

List of Tables

Preface
1. Table 1 Physical properties (room temperature values) of wide bandgap semi...
Chapter 2
1. Table 2.1 Indicating substrate characteristics beyond which significant fina...
2. Table 2.2 Cost considerations for SiC bulk growth.
Chapter 3
1. Table 3.1 Properties of silicon (Si) and carbon (C) host atoms and nitrogen ...
2. Table 3.2 Glide systems in hexagonal lattice (as given in textbook from Hull...
Chapter 4
1. Table 4.1 SiC epitaxial growth reactor comparisons.
Chapter 5
1. Table 5.1 Physical properties of Si, 3C‐SiC, 6H‐SiC, and 4H‐SiC [3–13].
2. Table 5.2 Recent results on 3C‐SiC MOSFET fabrication.
3. Table 5.3 Gate oxidation processes for the four 3C‐SiC/Si lateral MOS capaci...
Chapter 6
1. Table 6.1 Transition metal impurities in SiC–parameters identified by DLTS.
2. Table 6.2 Transition metal impurities in SiC–parameters identified by DLTS.
3. Table 6.3 Other impurities in SiC–parameters identified by DLTS.
Chapter 7
1. Table 7.1g·b values for dislocations from 1 to 6 in Figure 7.9.
Chapter 8
1. Table 8.1 Parameters for dislocation flow between veins.
Chapter 10
1. Table 10.1 Comparison of specific contact resistances : MLG ohmic contacts v...
Chapter 11
1. Table 11.1 Calculation of potential price/Amp for 20 A max rated SiC chips a...
Chapter 13
1. Table 13.1 AC and DC Voltages of the 3‐phase DC–AC PWM inverter in the case ...
2. Table 13.2 Results of the calculation of the total loss per arm for a 100 kV...
Chapter 14
1. Table 14.1 Thermomechanical material data.
Chapter 16
1. Table 16.1 Major specifications.
2. Table 16.2 Specifications of FCVCU.
Chapter 17
1. Table 17.1 Position of ZPLs and the ground state zero‐field splittings (ZFS)...
2. Table 17.2 Position of ZPLs and ground state zero‐field splittings (ZFS) of ...
3. Table 17.3 Experimental (exp) and calculated (DFT) values ofg, D parameters ...
Chapter 18
1. Table 18.1 Electrical properties (measured at room temperature using a home‐...
Chapter 19
1. Table 19.1 Material properties of substrates for GaN epitaxy.
Chapter 20
1. Table 20.1 Classification of diamond.
Chapter 21
1. Table 21.1. Diamond diodes.
2. Table 21.2 Diamond switching devices.
Chapter 22
1. Table 22.1 Comparison of material properties between Si, SiC, GaN, and β‐Ga₂

List of Illustrations

Preface
1. Figure 1 Relation of the on‐resistance and the breakdown voltage of a power ...
Chapter 1
1. Figure 1.1 Schematics of (a) physical vapor transport (PVT) growth reactor a...
2. Figure 1.2 Differential interference contrast (DIC) optical microscopy image...
3. Figure 1.3 Reflection X‐ray topographs from the three regions at the growth ...
4. Figure 1.4 Reflection X‐ray topographs of the growth front in the diffractio...
5. Figure 1.5 Cross‐sectional X‐ray topographs for diffraction condition g = 11
6. Figure 1.6 Cross‐sectional X‐ray topographs for diffraction conditions (a) g
7. Figure 1.7 Wider‐area transmission X‐ray topograph for diffraction condition...
8. Figure 1.8 Schematics of temporal change of BPD distribution in a 4H‐SiC cry...
9. Figure 1.9 Transmission X‐ray topographs for diffraction conditions (a) g = ...
10. Figure 1.10 Variations of (a) peak position of Raman‐active E ₂ mode around 7...
11. Figure 1.11 (a) Extended Raman microscopy image of bunched BPDs along the ba...
12. Figure 1.12 Variations of E ₂ mode peak position in growth direction measured...
13. Figure 1.13 Schematics of slicing geometry of a nitrogen‐doped 4H‐SiC crysta...
14. Figure 1.14 (a) Raman mapping image using longitudinal optical phonon–plasmo...
15. Figure 1.15 Raman microscopy images of region A, which is indicated by a red...
16. Figure 1.16 Reflection X‐ray topograph for diffraction condition g = 11 of ...
17. Figure 1.17 Reflection X‐ray topographs of BPD networks observed in region B...
18. Figure 1.18 Schematics of latent heat dissipation during PVT growth of 4H‐Si...
19. Figure 1.19 Schematic of introduction of BPDs at grown‐crystal/seed interfac...
20. Figure 1.20 Enlarged reflection X‐ray topograph for diffraction condition g ...
21. Figure 1.21 Schematic of the climb motion of a BPD toward the backside of th...
Chapter 2
1. Figure 2.1 Progression of demonstrated single‐crystal wafer diameter.
2. Figure 2.2 (a) Schematic of a SiC growth system, (b) schematic of gases pres...
3. Figure 2.3 Two differing methods for expanding SiC seed: (a) schematic of gr...
4. Figure 2.4 Images of six defect modes that are commonly observed in SiC grow...
5. Figure 2.5 Schematic illustrating overall kerf loss for wafer manufacture pr...
6. Figure 2.6 Schematic showing modern wire saw configuration: (a) configuratio...
7. Figure 2.7 (a) A 150 mm wafer shape obtained from an unoptimized cut, (b) 15...
8. Figure 2.8 Schematic of a CMP process.
Chapter 3
1. Figure 3.1 Schematic drawing of off‐cut angle α and off‐cut direction o...
2. Figure 3.2 Sketch of the BCF theory for 4H‐SiC homoepitaxy on the vicinal su...
3. Figure 3.3 Epitaxial growth rate vs. reciprocal growth temperature showing d...
4. Figure 3.4 Summary of reported doping‐induced misfit values as a function of...
5. Figure 3.5 Schematic drawing for illustrating the relationship between depth...
6. Figure 3.6 Examples for typical epilayer defects: appearance in dark field (...
7. Figure 3.7 Summary of room‐temperature luminescence data from stacking fault...
8. Figure 3.8 Diffusion constants for carbon vacancies (parallel to a‐ and c‐ax...
9. Figure 3.9 Calculated recombination carrier lifetime in a typical low N‐dope...
10. Figure 3.10 Trap energies and capture cross sections of intrinsic and extrin...
11. Figure 3.11 Typical DLTS spectrum for an as‐grown n‐type epilayer. Common po...
Chapter 4
1. Figure 4.1 SiC epi growth mechanism cartoon.
2. Figure 4.2 Schematic drawings of (a) cylindrical‐horizontal (shown with indu...
3. Figure 4.3 Detailed view of the 8–100 mm warm‐wall planetary VPE reactor inc...
4. Figure 4.4 Candela optical surface analyzer (CS20) defect map and typical de...
5. Figure 4.5 Candela optical surface analyzer (CS20) defect map for an example...
6. Figure 4.6 Epitaxial layer distributions for over 10 000 150 mm epitaxial wa...
7. Figure 4.7 Normalized plot of epitaxial area throughput vs. SiC warm‐wall re...
Chapter 5
1. Figure 5.1 Dependence of the growth rate with the Si/H2 ratio. This dependen...
2. Figure 5.2 (a) STEM cross‐section of a sample region where the generation pr...
3. Figure 5.3 (a) STEM cross‐section of two SFs crossing. (b) STEM cross‐sectio...
4. Figure 5.4 Stacking faults density vs. grown thickness. Different processes ...
5. Figure 5.5 The sequence of STEM images shows an APB and its effect on SFs. I...
6. Figure 5.6 Mean intrinsic strain in 3C‐SiC(100) as a function of the growth ...
7. Figure 5.7 Transmitted light images of free‐standing 2‐in. wafers with thick...
8. Figure 5.8 Growth‐setup for epitaxial sublimation growth and transfer‐proces...
9. Figure 5.9 Evolution of diameters for bulk 3C‐SiC crystals grown by epitaxia...
10. Figure 5.10 (a) Raman spectrum of typical sublimation grown material acquire...
11. Figure 5.11 Calculated supersaturation of the SiC₂ gas species for experimen...
12. Figure 5.12 (a) Evolution of protrusion dimensions for bulk 3C‐SiC layers wi...
13. Figure 5.13 Stacking fault (SF) density vs. thickness of SE‐grown 3C‐SiC lay...
14. Figure 5.14 Schematic of the new CVD growth process of the 3C‐SiC bulk wafer...
15. Figure 5.15 (a) Cross‐section SEM image of the 3C‐SiC wafer (about 200 μm). ...
16. Figure 5.16 FWHM of the X‐ray rocking curve as a function of film thickness ...
17. Figure 5.17 The 3C‐SiC 6 in. wafer after the total process. (a) The wafer on...
18. Figure 5.18 A cross‐sectional representation of a 3C‐SiC LDMOSFET.
19. Figure 5.19 Schematic representation of the “carbon cluster model”.
20. Figure 5.20 Oxide thickness as a function of oxidation time at 1150 °C for a...
21. Figure 5.21 Ideal and experimental (1 MHz) normalized C–V curves for MOS 1–4...
22. Figure 5.22 AFM images of Ni (a) and TiAlNi (b) ohmic contacts onto n‐ and p...
Chapter 6
1. Figure 6.1 (a) TCAD simulation for the forward current of a pin diode, assum...
2. Figure 6.2 Influence of carrier lifetime ( corresponds to maximum SRH gener...
3. Figure 6.3 From capacitance transients to DLTS spectrum: the capacitance is ...
4. Figure 6.4 Variation of the charge correction, E_corr, obtained for a double ...
5. Figure 6.5 (a) Atomic structure of perfect carbon vacancies at and sites...
6. Figure 6.6 Kohn–Sham electronic states at for the carbon vacancy at the cu...
7. Figure 6.7 Formation energy ( ) of the carbon vacancy at the cubic (a) and h...
8. Figure 6.8 Configuration coordinate diagram of defects in 4H‐SiC. Acceptor...
9. Figure 6.9 Arrhenius plots of electron emission rates for (=/0), (=/0), (
10. Figure 6.10 Capture kinetics measured for (=/0) and (=/0) transitions by L...
11. Figure 6.11 concentration vs depth profiles along the (a) and (b) dire...
12. Figure 6.12 Temperature dependence of diffusivity ( ) along the c directio...
13. Figure 6.13 Experimental characterization of charge state transitions. (a)...
14. Figure 6.14 (a) Simulation of a Schottky barrier diode using Sentaurus S‐dev...
15. Figure 6.15 Overview of all, by means of DLTS, directly measured trap levels...
16. Figure 6.16 Depiction of the table of elements: elements marked green have u...
17. Figure 6.17 Suggested positions for and in the 4H, 6H, 15R, and 3C polyt...
Chapter 7
1. Figure 7.1 (a) Back‐reflection X‐ray topograph images of closed‐core (smalle...
2. Figure 7.2 SWBXT transmission image (g = ) showing a diamond‐shaped BPD loo...
3. Figure 7.3 (a)–(c) Schematic of the formation of a single‐ended Frank–Read s...
4. Figure 7.4 Transmission topograph (g = 0004) shows dislocation contrast from...
5. Figure 7.5 (a) Illustration of the reaction between −c + a a...
6. Figure 7.6 (a) SWBXT transmission image of 0004 reflection; (b) a section to...
7. Figure 7.7 (a) Illustration of partial deflection of threading c + a disloca...
8. Figure 7.8 Transmission SWBXT images from 4H‐SiC crystals showing stacking f...
9. Figure 7.9 SWBXT images recorded from 4H‐SiC samples showing (a) a prismatic...
10. Figure 7.10 Correlation of wafer map (middle) showing the predicted distribu...
11. Figure 7.11 (a, c) X‐ray rocking curve peak position as a function of the be...
12. Figure 7.12 Grazing incidence X‐ray topographs recorded from the same area o...
13. Figure 7.13 Dislocations with unique shapes are observed in grazing incidenc...
14. Figure 7.14 (a, c) Grazing incidence X‐ray topographs of one or a pair of de...
15. Figure 7.15 (a) Cross section of the BPD etch pit along the line bisecting t...
16. Figure 7.16 SMBXT images showing the conversion of BPDs to TEDs. Burgers vec...
17. Figure 7.17 Schematics showing Shockley partial dislocations of different co...
18. Figure 7.18 Synchrotron X‐ray topographs ((a), (c), and (e)) and correspondi...
19. Figure 7.19 (a) SMBXT image recorded from an epilayer grown showing defects ...
20. Figure 7.20 Schematic diagram showing the formation mechanism of a HLA. (a)–...
21. Figure 7.21 X‐ray topographs and corresponding schematics of formation of in...
22. Figure 7.22 Grazing incidence X‐ray topographs of V and Y shape defects arou...
23. Figure 7.23 (a, c) The formation mechanism of V shape stacking fault during ...
Chapter 8
1. Figure 8.1 (a) An averaging area containing two edge dislocations with oppos...
2. Figure 8.2 (a) 2D crystal geometry and (b) initial distribution of the resol...
3. Figure 8.3 (a) Prescribed temperature field, (b) Thermal expansion coefficie...
4. Figure 8.4 Comparison between AH model and Groma model including a source te...
5. Figure 8.5 Dislocation organizes themselves into patterns as, e.g. cell stru...
6. Figure 8.6 (a) TEM micrograph showing walls of PSBs (dark) [57] and gliding ...
7. Figure 8.7 Initial CDD field values for two quasi‐discrete dislocation loops...
8. Figure 8.8 Initial CDD field values for a distribution of 50 dislocation loo...
9. Figure 8.9 Two mobile dislocation loops expansion in the channel.
10. Figure 8.10 Fifty mobile dislocation loops expansion in the channel.
11. Figure 8.11 Total line length vs. time. The two tangents denote the line len...
Chapter 9
1. Figure 9.1 Example for the sub‐threshold sweep hysteresis (SH) for a sweep s...
2. Figure 9.2 At the V _TH, the drain current shows negligibly tiny transient var...
3. Figure 9.3 Dependence of the amount of SH on the upward‐sweep starting volta...
4. Figure 9.4 Comparison of the amount of SH for different manufacturers (A, B,...
5. Figure 9.5 Evolution of the ΔV _TH during the application of a bipolar alterna...
6. Figure 9.6 (a) Decrease of the V _TH by the application of a negative gate bia...
7. Figure 9.7 Density of interface traps for similar planar (top) and trench (b...
8. Figure 9.8 Evolution of the voltage applied to the gate (V _G) and drain (V _D) ...
9. Figure 9.9 Voltage shift of a SiC–MOSFET due to constant gate bias stress [1...
10. Figure 9.10 (a) Measurement procedures and (b) their corresponding dependenc...
11. Figure 9.11 Drift of the threshold voltage over BTS time. denotes the chan...
12. Figure 9.12 (a) Calculated probability density function over activation ener...
13. Figure 9.13 Example normalized EDMR spectrum with zoomed in lines for better...
14. Figure 9.14 Atomistic model of 4H‐SiC with one layer of SiO on top.
15. Figure 9.15 Charged intrinsic electron trap with the spin density of the tra...
16. Figure 9.16 Example configuration of the hydroxyl E′ center in the neutral c...
Chapter 10
1. Figure 10.1 Scheme of epitaxial graphene on SiC. (a) Epitaxial graphene on S...
2. Figure 10.2 Partial intercalation of epitaxial graphene. (a) Scanning electr...
3. Figure 10.3 Epitaxial graphene as ohmic and Schottky contacts to SiC. (a) ML...
4. Figure 10.4 Monolithic epitaxial graphene/SiC transistor (GraSFET). (a) An a...
5. Figure 10.5 Monolithic integrated logic circuits. Logic inverter: circuit (a...
6. Figure 10.6 Detection of THz radiation with epitaxial graphene/SiC Schottky ...
Chapter 11
1. Figure 11.1 Cross‐sectional view of a vertical power DMOSFET cell.
2. Figure 11.2 A cross‐sectional view of a vertical power DMOSFET including act...
3. Figure 11.3 (a) Top‐view and (b) cross‐sectional view of three linear cells ...
4. Figure 11.4 A cross‐sectional view of 1.7 kV SiC vertical power DMOSFET.
5. Figure 11.5 A top‐view of a vertical power DMOSFET.
6. Figure 11.6 (Right) Mask #2: JFET mask and (left) a cross‐sectional view of ...
7. Figure 11.7 Mask #3: P‐well mask along with a cross‐sectional view of the wa...
8. Figure 11.8 Mask #4: N⁺ source mask along with a cross‐sectional view of...
9. Figure 11.9 Mask #5: P⁺ mask along with a cross‐sectional view of the wa...
10. Figure 11.10 Guard rings in the Mask #5.
11. Figure 11.11 All masks #2 to #5 together for forming JFET, P‐well, N⁺ so...
12. Figure 11.12 Formation of a graphite‐cap layer used for activation anneal.
13. Figure 11.13 Gate oxide growing on the surface.
14. Figure 11.14 Mask #6: gate poly for forming the polysilicon on the gate oxid...
15. Figure 11.15 Stack of oxide and nitride layer deposition.
16. Figure 11.16 Mask #7: Ohmic Metal for forming the metal on the source.
17. Figure 11.17 Mask #6 (Gate Poly) and #7 (Ohmic Metal).
18. Figure 11.18 Backside ohmic metal deposition.
19. Figure 11.19 Mask #8: Gate Runner.
20. Figure 11.20 Mask #7 (Gate Poly) and #8 (Gate Runner) together.
21. Figure 11.21 Mask #9: Overlayer Metal.
22. Figure 11.22 Mask #10 (Polyimide).
23. Figure 11.23 SEM images of nanopillars with (a) Cu, (b) Ni, and (c) Al metal...
24. Figure 11.24 Micro‐trenching side effect in a 4H‐SiC dry etching.
25. Figure 11.25 A waffle structure on a 4H‐SiC substrate formed by dry etching....
26. Figure 11.26 Improved bevel mesa formed with the optimized RIE condition....
27. Figure 11.27 Simulation profile of N implantation for forming N⁺ in 4H‐S...
28. Figure 11.28 Atomic force microscopy (AFM) images of Al⁺‐implanted (with...
29. Figure 11.29 The DLTS spectra obtained from Al⁺‐ room temperature implan...
30. Figure 11.30 Oxide thickness as a function of time and temperature for dry t...
31. Figure 11.31 Oxide thickness of 4H‐SiC for (a) Si‐face and (b) C‐face as a f...
32. Figure 11.32 D _it and V _fb values as a function of oxide thickness with no POA...
33. Figure 11.33 Reduction of the D _it over the entire range of energies within t...
34. Figure 11.34 Gas composition in the decomposition of N₂O at various temperat...
35. Figure 11.35 Time‐dependent threshold voltage shifts for (a) positive bias‐s...
36. Figure 11.36 The internal resistance components state‐of‐the‐arts SiC power ...
37. Figure 11.37 The X‐ray diffraction (XRD) spectra of the Ni contact lay...
38. Figure 11.38 Cross‐section of the MOSFET structure modeled.
Chapter 12
1. Figure 12.1 Energy band diagrams for a metal and a semiconductor.
2. Figure 12.2 Energy band diagrams for a metal–semiconductor system. (a) After...
3. Figure 12.3 Junction barrier Schottky diode structures [4]. On‐state current...
4. Figure 12.4 Measured temperature dependence of the reverse recovery characte...
5. Figure 12.5 Active power factor correction boost converter.
6. Figure 12.6 Comparison of the reverse recovery characteristics of the 4H‐SiC...
7. Figure 12.7 Forward bias curves of a 600 V 4H‐SiC Schottky diode as a functi...
8. Figure 12.8 SiC diode with merged p‐doped islands (MPS structure).
9. Figure 12.9 I–V characteristics for different temperatures of an 8 A/600 V M...
10. Figure 12.10 Cross‐sectional views of (a) planar JBS and (b) trench JBS diod...
11. Figure 12.11 Forward I–V characteristics of the planar structure and the tre...
12. Figure 12.12 Reverse I–V characteristics of the planar structure and the tre...
13. Figure 12.13 Simplified blocking structure represented as a PiN diode (a), a...
14. Figure 12.14 Specific R _ds, on as a function of breakdown voltage. Included a...
15. Figure 12.15 Simplified cross section of a 4H‐SiC DMOSFET.
16. Figure 12.16 4H‐SiC DMOSFET dimensions for on‐resistance calculations.
17. Figure 12.17 4H‐SiC DMOSFET resistance components. Assumptions: μ _n,ave ...
18. Figure 12.18 MOS channel mobility comparing samples with Ba interlayer to th...
19. Figure 12.19 Interface state density extracted from the high‐low C–V measure...
20. Figure 12.20 Simplified cross section of a 4H‐SiC trench MOSFET.
21. Figure 12.21 4H‐SiC trench MOSFET dimensions for on‐resistance calculations....
22. Figure 12.22 4H‐SiC trench MOSFET resistance components. Assumptions: μ
23. Figure 12.23 Cross section of the 4H‐SiC trench MOSFET with trench bottom pr...
24. Figure 12.24 Cross section of the 4H‐SiC trench MOSFET with double‐trench pr...
25. Figure 12.25 Cross section of the 4H‐SiC trench MOSFET with asymmetric prote...
26. Figure 12.26 Simplified cross section of a superjunction drift layer.
27. Figure 12.27 E‐field profile of a superjunction structure in blocking mode. ...
28. Figure 12.28 Specific on‐resistance of a function of breakdown voltage calcu...
29. Figure 12.29 Scanning electron microscopy (SEM) images of 4H‐SiC superjuncti...
30. Figure 12.30 On‐resistance and threshold voltage as a function of temperatur...
31. Figure 12.31 Cross section of (a) a MOSFET embedding SBD, (b) a conventional...
Chapter 13
1. Figure 13.1 Comparison of advanced Si and SiC devices.
2. Figure 13.2 Specific on‐resistance of SiC SJ‐MOSFET and SiC‐IGBT compared wi...
3. Figure 13.3 Structural comparison of unipolar 1.2 kV SiC‐MOSFET and over 10 ...
4. Figure 13.4 Theoretical breakdown voltage calculated from thickness and dopi...
5. Figure 13.5 Cross‐sectional structure of PiN diodes with mesa‐JTE structure....
6. Figure 13.6 Cross‐sectional structure of PiN diodes with inclined mesa struc...
7. Figure 13.7 Cross‐sectional structure of PiN diodes with multi‐zone JTE stru...
8. Figure 13.8 Cross‐sectional structure of a PiN diode with a space‐modulated ...
9. Figure 13.9 Relationship between the carrier life and the current density of...
10. Figure 13.10 Relationship between the carrier life and the current density o...
11. Figure 13.11 Dependence of carrier lifetime on drift layer thickness at each...
12. Figure 13.12 Carrier lifetime dependence of forward voltage at 100 A/cm² cal...
13. Figure 13.13 Relationship between the carrier lifetimes calculated from the ...
14. Figure 13.14 Dependence of the averaged density of electrons and holes in th...
15. Figure 13.15 Dependence of the distribution of electron and hole densities i...
16. Figure 13.16 The distribution of carrier density calculated from Eq. 13.30: ...
17. Figure 13.17 Hole density distribution of (a) PiN diode and (b) IGBT.
18. Figure 13.18 Forward characteristics of (a) PiN diode and (b) IGBT.
19. Figure 13.19 Vector diagram of 3‐phase AC.
20. Figure 13.20 Circuit diagram of 3‐phase DC‐AC PWM inverter.
21. Figure 13.21 Trade‐off between on‐state voltage and switching loss in PiN di...
22. Figure 13.22 Trade‐off between on‐state voltage and switching loss in IGBTs....
23. Figure 13.23 Reported Break down voltage vs. on-resistance at 100 A/cm² of I...
24. Figure 13.24 Cross‐sectional view of the SiC‐IGBT.
25. Figure 13.25 Trade‐off between on‐state voltage and switching loss in IGBTs....
26. Figure 13.26 16 kV SiC‐IGBT (8 mm × 8 mm) and reverse BV characteristics.
27. Figure 13.27 Pulsed on‐state I‐V characteristics of the 16 kV SiC‐IGBT.
28. Figure 13.28 Temperature dependence of forward characteristics at V _GE = 30 V...
29. Figure 13.29 Circuit configurations for switching measurements.
30. Figure 13.30 Turn‐off switching waveforms of an 8 mm × 8 mm n‐channel 16 kV ...
31. Figure 13.31 High power switching waveform of 4 16 kV SiC‐IGBTs and PiN diod...
32. Figure 13.32 Cross‐sectional image of over 20 kV class SiC‐IGBT.
33. Figure 13.33 Forward and reverse characteristics of higher‐than‐20 kV class ...
34. Figure 13.34 I–V curve comparison of ideal SiC‐IGBT, series of equivalent BV...
Chapter 14
1. Figure 14.1 Schematic temperature distribution after short‐circuit event of ...
2. Figure 14.2 Simulated R _DS,ON vs. short‐circuit time trade‐offs, base for sim...
3. Figure 14.3 Typical short‐circuit type 1 waveform of SiC trench MOSFET.
4. Figure 14.4 DIBL effect, V _GS,TH is lowered with higher drain‐source voltage....
5. Figure 14.5 Rising saturation currents I _D,sat with increased drain‐source vo...
6. Figure 14.6 SiC MOSFET: different kinds of short‐circuit destruction; Left: ...
7. Figure 14.7 Possible failure picture with gate‐source short after a long‐las...
8. Figure 14.8 Short‐circuit waveforms in different packages, V _DC = 800 V, V _GS ...
9. Figure 14.9 Impact of V _GS,TH hysteresis on short‐circuit.
10. Figure 14.10 Schematic surge‐current event (left) and corresponding I–V curv...
11. Figure 14.11 Surge‐current event at 1200 V/20 A rated SiC MPS diode (left) a...
12. Figure 14.12 MPS diode: schematic way of electrons around p‐island.
13. Figure 14.13 Simulated temperatures during a 10 ms surge‐current event with ...
14. Figure 14.14 Failure pictures after single‐event destructive surge‐current p...
15. Figure 14.15 Last pass surge‐current waveform of a 1200 V/20 A SiC MOSFET bo...
16. Figure 14.16 Surge‐current destruction behavior of 40 mΩ class, 1200 V SiC M...
17. Figure 14.17 Last pass surge waveform of a 1200 V/20 A SiC MOSFET in the thi...
18. Figure 14.18 Optical microscope image from chip backside (after removal of b...
19. Figure 14.19 Shell‐like crack at backside of the chip after doing 2570 pulse...
20. Figure 14.20 I/V curves of 220 A peak/10 ms sine‐shape repetitive surge curr...
21. Figure 14.21 Left: onset of avalanche breakdown in the active area of a SiC ...
22. Figure 14.22 Electroluminescence picture at breakdown of SiC MPS diode. Slig...
23. Figure 14.23 Unclamped‐inductive switching test circuit for diodes and schem...
24. Figure 14.24 Left: lastpass unclamped‐inductive switching pulse of an 8 A/12...
25. Figure 14.25 Unclamped‐inductive switching event of an 8 A/1200 V SiC MPS di...
26. Figure 14.26 Left: last‐pass energy and currents of an 8 A/1200 V SiC MPS di...
27. Figure 14.27 Unclamped‐inductive switching with last‐pass energy of a 40 mΩ/...
28. Figure 14.28 Unclamped‐inductive switching event of 40 mΩ/1200 V SiC MOSFET,...
29. Figure 14.29 Left: Repetitive unclamped‐inductive switching event of 1200 V ...
30. Figure 14.30 Cosmic‐ray failure of a SiC MPS diode.
31. Figure 14.31 Comparison of Cosmic ray failure rates for Si IGBTs and SiC MOS...
32. Figure 14.32 Forward characteristics of the inverse diode of the SiC MOSFET ...
33. Figure 14.33 Calibration function V _j (T) for the 1200 V SiC MOSFET IMW120R04...
34. Figure 14.34 Threshold voltage hysteresis depending on V _GS before measuremen...
35. Figure 14.35 Bias temperature instability test of different manufacturers. 5...
36. Figure 14.36 Power‐cycling setup for SiC MOSFET with V _SD‐method (a) schemati...
37. Figure 14.37 Sintered Ag‐layer and sintered Cu‐layer.
38. Figure 14.38 Progress in power‐cycling capability, comparison of Si and SiC....
39. Figure 14.39 Power cycling of SiC Schottky diodes packaged with “.XT technol...
40. Figure 14.40 Sintered Cu‐foil on top of a SiC device.
41. Figure 14.41 AlCu ribbons for possible replacement of Al wires. (a) top view...
Chapter 15
1. Figure 15.1 Impact of the SiC properties on the system.
2. Figure 15.2 Application ranges for SiC devices. Data points are calculated t...
3. Figure 15.3 Application ranges for SiC devices in competition with silicon I...
4. Figure 15.4 Trends in bridge‐less power factor correction (PFC) stages.
5. Figure 15.5 Technology comparison between silicon, SiC, and GaN devices.
6. Figure 15.6 PETT topology according to [11, 12], with the primary‐side low‐f...
7. Figure 15.7 Advantages of a novel SiC‐based technology for induction heating...
8. Figure 15.8 (a) Transformer‐less single‐phase PV converter with an H5 topolo...
9. Figure 15.9 Hybrid HVDC breaker according to [63].
10. Figure 15.10 Traction converter and motor of a Shinkansen N700 and their imp...
Chapter 16
1. Figure 16.1 Milestones in popularizing electrified vehicles (announced in De...
2. Figure 16.2 Rate of popularization of Toyota's electrified vehicles (announc...
3. Figure 16.3 The ratio of the electrical loss of power control unit (PCU).
4. Figure 16.4 SORA: Tokyo Toei FC bus.
5. Figure 16.5 Heavy‐duty FC trucks @LA Port.
6. Figure 16.6 Conventional electric power plant (2009 model FCV).
7. Figure 16.7 New FCV electric power plant.
8. Figure 16.8 FCVCU circuit.
9. Figure 16.9 Power loss in semiconductor device.
10. Figure 16.10 Switching loss in semiconductor device.
11. Figure 16.11 Switching waveform.
12. Figure 16.12 Image of drive phase control.
13. Figure 16.13 Effects of drive phase control.
14. Figure 16.14 Downsizing effect on FCVCU.
15. Figure 16.15 Power loss comparison with conventional VCU.
16. Figure 16.16 Schematic of voltage waveform resulting from voltage boost.
17. Figure 16.17 Change in higher harmonic trapezoidal wave resulting from high‐...
18. Figure 16.18 High‐voltage cable layout of FC stack and FCVCU.
19. Figure 16.19 Cross section of FCVCU.
20. Figure 16.20 FCVCU components.
21. Figure 16.21 Structure of 2‐in‐1 power card.
22. Figure 16.22 TLP bonding for power module.
23. Figure 16.23 Ni micro‐plating bonding (NMPB) technology. (A) Structure of 2‐...
24. Figure 16.24 Inverter circuits. (a) Conventional half bridge inverter circui...
25. Figure 16.25 Three‐phase inverter circuit for EVs/HEVs.
26. Figure 16.26 Double‐pulse test circuit.
27. Figure 16.27 Schematic waveforms in double‐pulse test.
28. Figure 16.28 Schematic waveforms of the turn‐off characteristics.
29. Figure 16.29 Schematic waveforms of the turn‐on characteristics.
30. Figure 16.30 Conventional gate driver circuit.
31. Figure 16.31 Gate driver circuit with speed‐up capacitor.
32. Figure 16.32 Gate driver circuit with gate current paths separated by diodes...
33. Figure 16.33 Gate driver circuit with gate current paths separated by output...
34. Figure 16.34 Turn‐off loss as a function of maximum V _ds.
35. Figure 16.35 Turn‐on loss as a function of maximum I _d.
36. Figure 16.36 Device characteristics comparisons between the Si‐IGBT and SiC‐...
37. Figure 16.37 (a) An SiC‐MOSFET wafer with φ = 150 mm and (b) an 8 mm × 8 mm ...
38. Figure 16.38 3D sketch of (a) the conventional structure and (b) the propose...
39. Figure 16.39 Relationship between the on‐resistance and the Deep‐P pitch. Th...
40. Figure 16.40 Dependence of the JFET resistance and gate oxide field on the g...
41. Figure 16.41 Electric potentials of the (a) front view of the conventional s...
42. Figure 16.42 Deep‐P gap dependences of C _gd and JFET resistance.
43. Figure 16.43 On‐ and off‐state characteristics of the fabricated MOSFET with...
44. Figure 16.44 Plot of the breakdown voltage vs. the on‐resistance for 4H‐SiC ...
45. Figure 16.45 Measured results for C _gd and C _ds of the conventional and presen...
46. Figure 16.46 Measured gate charges of the (a) presented and (b) conventional...
47. Figure 16.47 Double‐pulse waveforms of the (a) turn‐on and (b) turn‐off of t...
48. Figure 16.48 (a) Drain current dependence of E _on + E _off (V _d = 650 V; V _g = −5...
49. Figure 16.49 Schematic cross‐sectional illustrations of the (a) PN diode, (b...
50. Figure 16.50 Forward voltage degradation as a function of the current densit...
51. Figure 16.51 Forward voltage degradation of V _g = 0 V and V _g = −5 V as a func...
52. Figure 16.52 Forward voltage degradation of V _g = 0 V and V _g = −5 V as a func...
Chapter 17
1. Figure 17.1 Important polytypes of SiC except for 2H. 2H SiC consists of onl...
2. Figure 17.2 The considered defects in SiC. TM stands for transition metal io...
Chapter 18
1. Figure 18.1 Scheme of the HVPE method; horizontal configuration is presented...
2. Figure 18.2 (a) Radius of curvature (bending of crystallographic planes) as ...
3. Figure 18.3 (a) Morphology of 1‐mm‐thick GaN grown by HVPE on MOVPE‐GaN/sapp...
4. Figure 18.4 Scheme of the ammonothermal method (a) acidic; (b) basic.
5. Figure 18.5 (a) Scheme of HNPS growth presented by Grzegory et al. [39]; the...
6. Figure 18.6 Basic ammonothermal growth method (two processes); (a) part 1 – ...
7. Figure 18.7 (a) Morphology of Am‐GaN grown in the −c‐direction; (b) synchrot...
8. Figure 18.8 Am‐GaN substrates prepared by IHPP PAS (a) n‐type with a carrier...
9. Figure 18.9 Star‐like defects in highly conductive Am‐GaN: (a) image from an...
10. Figure 18.10 Am‐GaN crystal grown in one crystallization run: 6‐mm‐thick and...
11. Figure 18.11 (a) Typical morphology of HVPE‐GaN grown on Am‐GaN seed; one hi...
12. Figure 18.12 (a) Three‐mm‐thick HVPE‐GaN grown on Am‐GaN; equilibrium hexago...
13. Figure 18.13 (a) Calculated Von Mises stress distribution in HVPE‐GaN deposi...
14. Figure 18.14 Edges of HVPE‐GaN crystals grown (a) without Mo elements in the...
15. Figure 18.15 (a) Morphology of HVPE‐GaN:Si; hillock growth mode; grid 1 mm; ...
16. Figure 18.16 (a) Morphology of HVPE‐GaN:C; (b) resistivity and hole concentr...
17. Figure 18.17 Morphologies of (a) HVPE‐GaN:Fe; (b) HVPE‐GaN:Mn.
18. Figure 18.18 Resistivity as a function of inverse of temperature for HVPE‐Ga...
Chapter 19
1. Figure 19.1 Epitaxial structure of GaN on Si substrate.
2. Figure 19.2 Structures of buffer layers for GaN on Si substrate. (a) Step‐gr...
3. Figure 19.3 Polarization vectors of III‐N semiconductor in the tetrahedron s...
4. Figure 19.4 Charge distribution and band diagram of AlGaN/GaN structure.
5. Figure 19.5 Sequence of GaN‐HFET device process showing (a), (b) ohmic metal...
6. Figure 19.6 Band diagram of AlGaN/GaN structure with Schottky gate.
7. Figure 19.7 Schematic cross‐section of GaN‐GIT [69].
8. Figure 19.8 Band diagram of GaN‐GIT at the gate bias of 0 V [69].
9. Figure 19.9 Cross‐sectional structure of GaN‐GIT showing operational princip...
10. Figure 19.10 Measured – characteristics of fabricated GaN‐GIT on Si substr...
11. Figure 19.11 Measured on‐state – characteristics of fabricated GaN‐GIT on ...
12. Figure 19.12 Measured off‐state – characteristics of fabricated GaN‐GIT on...
13. Figure 19.13 Breakdown voltages of fabricated GaN‐GITs on Si substrate for v...
14. Figure 19.14 Measured recovery characteristics of GaN‐GIT in diode‐mode oper...
15. Figure 19.15 Operations of a IGBT‐based inverter and GaN‐based one showing f...
16. Figure 19.16 Measured power‐conversion efficiency of three‐phase inverter wi...
17. Figure 19.17 The analysis of operating losses in the GaN inverter system com...
18. Figure 19.18 Schematic cross‐section of GaN‐GITs integrated into one chip wi...
19. Figure 19.19 Photograph of the fabricated 6‐in‐1 GaN three‐phase inverter IC...
20. Figure 19.20 Circuit diagram of the DC/DC converter IC with integrated GaN g...
21. Figure 19.21 Photograph of the fabricated DC/DC IC in which two GaN power tr...
22. Figure 19.22 Schematic cross‐section of E‐mode and D‐mode GaN HFETs integrat...
Chapter 20
1. Figure 20.1 The phase diagram of carbon (restricted to the two solid allotro...
2. Figure 20.2 Schematic representations of three common HPHT growth setups: (a...
3. Figure 20.3 Photos of typical growth setups. (a, b) BARS setup with (1) clam...
4. Figure 20.4 Schema of a high‐pressure growth cell used in a BARS setup. (1) ...
5. Figure 20.5 Cubo‐octahedral‐shaped diamond crystals grown by the temperature...
6. Figure 20.6 Diamond plate cut in (001) orientation from a IIa‐type HPHT crys...
7. Figure 20.7 Boron‐doped diamond crystals grown by the HPHT technique. The va...
8. Figure 20.8 (a) A simple schema showing the principal elements of CVD diamon...
9. Figure 20.9 C–H–O diagram for the deposition of diamond. Highlighted in red ...
10. Figure 20.10 Schemata of different reactors: (a) hot filament CVD, (b) DC pl...
11. Figure 20.11 Simulations of the electric field distribution for different mi...
12. Figure 20.12 Correlation between temperature of the gas phase in the activat...
13. Figure 20.13 Schema of (a) a microwave plasma discharge above a substrate an...
14. Figure 20.14 Scanning electron micrographs of the surface of polycrystalline...
15. Figure 20.15 Different approaches for the lateral increase in crystal size b...
16. Figure 20.16 Heteroepitaxial diamond growth on different substrate materials...
17. Figure 20.17 Schema describing the typical phenomenology of BEN on Ir.(a...
18. Figure 20.18 Detailed description of the IBI‐BLG mechanism. (a) Atomic force...
19. Figure 20.19 Schema of the different stages of epitaxial diamond growth on I...
20. Figure 20.20 Variation of (a) Raman line width and (b) etch pit density (EPD
21. Figure 20.21 (a) Thermal stress σ _xx in diamond layers on different subs...
22. Figure 20.22 (a) Free‐standing unpolished single crystal diamond wafer with ...
23. Figure 20.23 Variation of in‐plane stress with deposition temperature for gr...
24. Figure 20.24 Sequence of process steps of the microneedle concept. (a) Thin ...
25. Figure 20.25 (a) Heteroepitaxial diamond layer after 2‐hour growth (partial ...
26. Figure 20.26 Etch pits generated to reveal densities of threading dislocatio...
Chapter 21
1. Figure 21.1 Electrical and thermal characteristics of diamond and other semi...
2. Figure 21.2 Progress made in the development of artificial diamond.. GE,...
3. Figure 21.3 Example of bulk crystal with 10‐mm thickness grown on 10 mm² squ...
4. Figure 21.4 Tiled clone with 20‐mm edge, where four single‐crystal diamond s...
5. Figure 21.5 Typical process windows for phosphorus and boron doping of CVD d...
6. Figure 21.6 Typical temperature dependence of carrier concentration and mobi...
7. Figure 21.7 Changes of the barrier width of semiconductor/metal interface an...
8. Figure 21.8 Resistivity as a function of effective B doping concentration (N
9. Figure 21.9 Electrical properties of diamond Schottky barrier diodes: (a) Di...
10. Figure 21.10 Distribution of SBD parameters of Diode A (normal epitaxy) and ...
11. Figure 21.11 IV characteristics of diamond Schottky barrier diode and packag...
12. Figure 21.12 (a) EBIC image of diamond pVSBD with floating metal guard rings...
13. Figure 21.13 IDS‐VDS characteristics of diamond MESFET operated at 450 °C an...
Chapter 22
1. Figure 22.1 Atomic unit cell of β‐Ga₂O₃.
2. Figure 22.2 Schematic of ozone/RF‐plasma MBE system illustrating Ga₂O₃ thin ...
3. Figure 22.3 Schematic of atmospheric‐pressure HVPE system for Ga₂O₃ growth....
4. Figure 22.4 Schematic cross section of vertical Ga₂O₃ SBD structure.
5. Figure 22.5 Schematic cross section of vertical Ga₂O₃ FP‐SBD structure.
6. Figure 22.6 Schematic cross section of vertical Ga₂O₃ fin‐channel SBD struct...
7. Figure 22.7 (a) Schematic cross section and (b) optical micrograph of Ga₂O₃ ...
8. Figure 22.8 DC output characteristics of Ga₂O₃ MESFET.
9. Figure 22.9 Schematic cross section of D‐mode Ga₂O₃ MOSFET structure fabrica...
10. Figure 22.10 DC output characteristics of D‐mode Ga₂O₃ MOSFET.
11. Figure 22.11 Schematic cross section of Ga₂O₃ FP‐MOSFET structure.
12. Figure 22.12 Schematic cross section of Ga₂O₃ MOSFET structure with N‐doped ...
13. Figure 22.13 Schematic cross section of vertical D‐mode Ga₂O₃ MOSFET structu...

Wide Bandgap Semiconductors for Power Electronics

Materials, Devices, Applications

Wide Bandgap Semiconductors for Power Electronics

Materials, Devices, Applications