reading

Cover
Title Page
Preface
Acknowledgements
Foreword
About the Companion Website
1 Introduction to DSP
1. 1.1 Introduction
2. 1.2 Multicore processors
3. 1.3 Key applications of high‐performance multicore devices
4. 1.4 FPGAs, Multicore DSPs, GPUs and Multicore CPUs
5. 1.5 Challenges faced for programming a multicore processor
6. 1.6 Texas Instruments DSP roadmap
7. 1.7 Conclusion
8. References
2 The TMS320C66x architecture overview
1. 2.1 Overview
2. 2.2 The CPU
3. 2.3 Single instruction, multiple data (SIMD) instructions
4. 2.4 The KeyStone memory
5. 2.5 Peripherals
6. 2.6 Conclusion
7. References
3 Software development tools and the TMS320C6678 EVM
1. 3.1 Introduction
2. 3.2 Software development tools
3. 3.3 Hardware development tools
4. 3.4 Laboratory experiments based on the C6678 EVM: introduction to Code Composer Studio (CCS)
5. 3.5 Loading different applications to different cores
6. 3.6 Conclusion
7. References
4 Numerical issues
1. 4.1 Introduction
2. 4.2 Fixed‐ and floating‐point representations
3. 4.3 Dynamic range and accuracy
4. 4.4 Laboratory exercise
5. 4.5 Conclusion
6. References
5 Software optimisation
1. 5.1 Introduction
2. 5.2 Hindrance to software scalability for a multicore processor
3. 5.3 Single‐core code optimisation procedure
4. 5.4 Interfacing C with intrinsics, linear assembly and assembly
5. 5.5 Assembly optimisation
6. 5.6 Software pipelining
7. 5.7 Linear assembly
8. 5.8 Avoiding memory banks
9. 5.9 Optimisation using the tools
10. 5.10 Laboratory experiments
11. 5.11 Conclusion
12. References
6 The TMS320C66x interrupts
1. 6.1 Introduction
2. 6.2 The interrupt controller
3. 6.3 Laboratory experiment
4. 6.4 Conclusion
5. References
7 Real‐time operating system: TI‐RTOS
1. 7.1 Introduction
2. 7.2 TI‐RTOS
3. 7.3 Real‐time scheduling
4. 7.4 Dynamic memory management
5. 7.5 Laboratory experiments
6. 7.6 Conclusion
7. References
8 Enhanced Direct Memory Access (EDMA3) controller
1. 8.1 Introduction
2. 8.2 Type of DMAs available
3. 8.3 EDMA controllers architecture
4. 8.4 Parameter RAM (PaRAM)
5. 8.5 Transfer synchronisation dimensions
6. 8.6 Simple EDMA transfer
7. 8.7 Chaining EDMA transfers
8. 8.8 Linked EDMAs
9. 8.9 Laboratory experiments
10. 8.10 Conclusion
11. References
9 Inter‐Processor Communication (IPC)
1. 9.1 Introduction
2. 9.2 Texas Instruments IPC
3. 9.3 Notify module
4. 9.4 MessageQ
5. 9.5 ListMP module
6. 9.6 GateMP module
7. 9.7 Multi‐processor Memory Allocation: HeapBufMP, HeapMemMP and HeapMultiBufMP
8. 9.8 Transport mechanisms for the IPC
9. 9.9 Laboratory experiments with KeyStone I
10. 9.10 Laboratory experiments with KeyStone II
11. 9.11 Conclusion
12. References
10 Single and multicore debugging
1. 10.1 Introduction
2. 10.2 Software and hardware debugging
3. 10.3 Debug architecture
4. 10.4 Advanced Event Triggering
5. 10.5 Unified Instrumentation Architecture
6. 10.6 Debugging with the System Analyzer tools
7. 10.7 Instrumentation with TI‐RTOS and CCS
8. 10.8 Laboratory sessions
9. 10.9 Conclusion
10. References
11 Bootloader for KeyStone I and KeyStone II
1. 11.1 Introduction
2. 11.2 How to start the boot process
3. 11.3 The boot process
4. 11.4 ROM Bootloader (RBL)
5. 11.5 Boot process
6. 11.6 Laboratory experiment 1
7. 11.7 Laboratory experiment 2
8. 11.8 TFTP boot with a host‐mounted Network File System (NFS) server – NFS booting
9. 11.9 Conclusion
10. References
12 Introduction to OpenMP
1. 12.1 Introduction to OpenMP
2. 12.2 Directive formats
3. 12.3 Forking region
4. 12.4 Work‐sharing constructs
5. 12.5 Environment variables and library functions
6. 12.6 Synchronisation constructs
7. 12.7 OpenMP accelerator model
8. 12.8 Laboratory experiments
9. 12.9 Conclusion
10. References
13 Introduction to OpenCL for the KeyStone II
1. 13.1 Introduction
2. 13.2 Operation of OpenCL
3. 13.3 Command queue
4. 13.4 Kernel declaration
5. 13.5 How do the kernels access data?
6. 13.6 OpenCL memory model for the KeyStone
7. 13.7 Synchronisation
8. 13.8 Basic debugging profiling
9. 13.9 OpenMP dispatch from OpenCL
10. 13.10 Building the OpenCL project
11. 13.11 Laboratory experiments
12. 13.12 Conclusion
13. References
14 Multicore Navigator
1. 14.1 Introduction
2. 14.2 Navigator architecture
3. 14.3 Complete functionality of the Navigator
4. 14.4 Laboratory experiment
5. 14.5 Conclusion
6. References
15 FIR filter implementation
1. 15.1 Introduction
2. 15.2 Properties of an FIR filter
3. 15.3 Design procedure
4. 15.4 Laboratory experiments
5. 15.5 Conclusion
6. References
16 IIR filter implementation
1. 16.1 Introduction
2. 16.2 Design procedure
3. 16.3 Coefficients calculation
4. 16.4 IIR filter implementation
5. 16.5 Laboratory experiment
6. 16.6 Conclusion
7. Reference
17 Adaptive filter implementation
1. 17.1 Introduction
2. 17.2 Mean square error
3. 17.3 Least mean square
4. 17.4 Implementation of an adaptive filter using the LMS algorithm
5. 17.5 Implementation using linear assembly
6. 17.6 Implementation in C language with compiler switches
7. 17.7 Laboratory experiment
8. 17.8 Conclusion
9. References
18 FFT implementation
1. 18.1 Introduction
2. 18.2 FFT algorithm
3. 18.3 FFT implementation
4. 18.4 Laboratory experiment
5. 18.5 Conclusion
6. References
19 Hough transform
1. 19.1 Introduction
2. 19.2 Theory
3. 19.3 Limits of r and θ
4. 19.4 Hough transform implementation
5. 19.5 Laboratory experiment
6. 19.6 Conclusion
7. References
20 Stereo vision implementation
1. 20.1 Introduction
2. 20.2 Algorithm for performing depth calculation
3. 20.3 Cost functions
4. 20.4 Implementation
5. 20.5 Conclusion
6. References
Index
End User License Agreement

List of Tables

Chapter 01
1. Table 1.1 Top 10 supercomputers, November 2016 [9]
2. Table 1.2 Pros and cons of multicore SoCs and FPGA SoCs [12]
3. Table 1.3 Main TI family of embedded processors
Chapter 02
1. Table 2.1 KeyStone I family
2. Table 2.2 KeyStone II family
3. Table 2.3 Possible 40‐/64‐bit register pair combinations
4. Table 2.4 Possible 128‐bit register pair combinations
5. Table 2.5 Fixed‐point multiplications per unit
6. Table 2.6 Floating‐point multiplications per unit
7. Table 2.7 SIMD examples
8. Table 2.8 TMS320C66x control registers [5]
9. Table 2.9 Local L2 memory for all TMS320C6678 cores
10. Table 2.10 Timer modes
Chapter 03
1. Table 3.1 Common compiler options
2. Table 3.2 Common assembler options
3. Table 3.3 Frequently used options for the linker
Chapter 04
1. Table 4.1 Examples of fixed‐ and floating‐point applications
2. Table 4.2 4‐bit unsigned integer numbers
3. Table 4.3 4‐bit signed integer numbers
4. Table 4.4 4‐bit fractional numbers
5. Table 4.5 Special numbers
6. Table 4.6 Numerical format used for the KeyStone
Chapter 05
1. Table 5.1 Optimisation levels of the optimising compiler
2. Table 5.2 Parser and optimiser options summary
3. Table 5.3 Registers use
4. Table 5.4 Iteration interval table for an FIR filter
5. Table 5.5 Iteration interval table for an FIR filter
6. Table 5.6 Iteration interval table for an FIR filter
7. Table 5.7 Different sections of the code
8. Table 5.8 Resource allocation
9. Table 5.9 Register allocation
10. Table 5.10 Scheduling table
11. Table 5.11 Scheduling table
12. Table 5.12 Scheduling table
Chapter 06
1. Table 6.1 Interrupt sources and priority
2. Table 6.2 CIC0 event inputs (secondary interrupts for TMS320C66x CorePacs) [1]
3. Table 6.3 Memory location of the CIC0 and CIC1 for the TMS320C6678 [1]
4. Table 6.4 CIC register offsets
Chapter 07
1. Table 7.1 Swi APIs
2. Table 7.2 Comparison of thread characteristics for the KeyStone devices [1]
Chapter 08
1. Table 8.1 Events associated with the EDMA3CC0 for the TMS320C6678
2. Table 8.2 Events associated with the EDMA3CC1 for the TMS320C6678 [2]
3. Table 8.3 Events associated with the EDMA3CC2 for the TMS320C6678 [3]
Chapter 09
1. Table 9.1 Modules used by the IPC [1]
2. Table 9.2 Main MessageQ functions
3. Table 9.3 Functions for the ListMP module
4. Table 9.4 Local and remote protection levels
5. Table 9.5 Example showing how to use GateMP
Chapter 10
1. Table 10.1 Trace actions description
2. Table 10.2 xdc.runtime package
3. Table 10.3 Different categories available
4. Table 10.4 RTOS Analyzer functions
5. Table 10.5 System Analyzer commands
6. Table 10.6 Comparison between a few debugging techniques
Chapter 11
1. Table 11.1 Reset types for the KeyStone I [3]
2. Table 11.2 Reset types for the KeyStone II [1]
3. Table 11.3 Reset types summary for both KeyStone I and II
4. Table 11.4 Boot Parameter Table Common Parameters (TMS320C6678) [3]
5. Table 11.5 EMIF16 boot mode parameter table (TMS320C6678) [3]
6. Table 11.6 SPI device configuration bit fields
7. Table 11.7 SPI device configuration field descriptions (TMS320CC6678) [3]
8. Table 11.8 EMIF16 boot parameter table common parameters (66AK2H14/12/06)
9. Table 11.9 EMIF16 boot parameter table (TMS320C66AK2H14/12/06)
10. Table 11.10 SPI boot parameter table (TMS32066AK2H14/12/06) [1]
11. Table 11.11 Bootloader Section in L2 SRAM
12. Table 11.12 Boot mode for the C6678 EVM [7]
13. Table 11.13 Boot mode switches
14. Table 11.14 Steps required for booting the EVM
15. Table 11.15 KeyStone II boot examples [11]
Chapter 12
1. Table 12.1 Clauses and descriptions
2. Table 12.2 Pragmas where the clauses can be used
3. Table 12.3 Environment variables used
Chapter 13
1. Table 13.1 Some device information
2. Table 13.2 Different levels for the callback function
3. Table 13.3 getProfilingInfo parameters
Chapter 14
1. Table 14.1 PKDMA channel map
2. Table 14.2 Rx DMA channel Config region registers
3. Table 14.3 Host packet descriptor layout
4. Table 14.4 Host buffer descriptor layout
5. Table 14.5 Description memory setup region registers [10]
6. Table 14.6 Peek registers
7. Table 14.7 Queue map for the KeyStone I
8. Table 14.8 Queue map for the KeyStone II
Chapter 15
1. Table 15.1 Conditions for linear phase
2. Table 15.2 Window features
3. Table 15.3 FIR coefficients converted into Q15 format
Chapter 18
1. Table 18.1 DFT calculation for every frequency bin
Chapter 20
1. Table 20.1 Most common cost functions

List of Illustrations

Chapter 01
1. Figure 1.1 The impact of the serial code that cannot be parallelised on the performance.
2. Figure 1.2 Amdahl’s law [7].
3. Figure 1.3 The inter‐processor communication effect.
4. Figure 1.4 Example where three cores can perform the task required by the parallel code.
5. Figure 1.5 Example where cores are processing different algorithms.
6. Figure 1.6 Example when serial code and parallel code are processed simultaneously.
7. Figure 1.7 Texas Instruments DSPs.
8. Figure 1.8 Performance comparison.
9. Figure 1.9 Texas Instruments DSP roadmap (courtesy Texas Instruments).
Chapter 02
1. Figure 2.1 Texas Instruments (TI) digital signal processor (DSP) roadmap.
2. Figure 2.2 KeyStone I architecture [3].
3. Figure 2.3 KeyStone II architecture [4].
4. Figure 2.4 TMS320C66x CPU block diagram.
5. Figure 2.5 TMS320C66x CPU data path and control.
6. Figure 2.6 Address cross paths.
7. Figure 2.7 Instructions completing in the same cycle.
8. Figure 2.8 Four‐way SIMD operation.
9. Figure 2.9 Simplified memory structure for KeyStone.
10. Figure 2.10 Memory structure, including the MPAX for KeyStone.
11. Figure 2.11 Example of cores accessing their local or other local memories.
12. Figure 2.12 Example showing the use of MPAX.
13. Figure 2.13 Memory topology for the TMS320C6678.
Chapter 03
1. Figure 3.1 Hardware and software development tools.
2. Figure 3.2 Texas Instruments’ software ecosystem [3].
3. Figure 3.3 Basic development tools.
4. Figure 3.4 Excerpt of command file for the TMS320C6678 EVM (C6678.cmd).
5. Figure 3.5 RTSC tools [6].
6. Figure 3.6 Entering a linker command file.
7. Figure 3.7 Platform selection.
8. Figure 3.8 Creating a new platform.
9. Figure 3.9 Selecting the device family and device name for the new platform.
10. Figure 3.10 Device page.
11. Figure 3.11 How to modify the new platform.
12. Figure 3.12 Output when a successful platform is generated.
13. Figure 3.13 Selecting the new platform for the project.
14. Figure 3.14 Multicore Software Development Kit (MCSDK) [9, 10].
15. Figure 3.15 The TMS320C6678 and the KeyStone II EVMs. (a) TMS320C6678 EVM without and with an emulator; (b) KeyStone II EVM without and with an emulator.
16. Figure 3.16 EVM layout. (a) TMS320C6678L [14]; (b) KeyStone II [15].
17. Figure 3.17 Code Composer Studio (CCS).
18. Figure 3.18 The TMS320C6678 EVM.
19. Figure 3.19 CCS download page.
20. Figure 3.20 Registration with myTI.
21. Figure 3.21 CCS download.
22. Figure 3.22 CCS starting window.
23. Figure 3.23 Selecting a workspace location.
24. Figure 3.24 Lab1 basic project settings.
25. Figure 3.25 Lab1 advanced project settings.
26. Figure 3.26 Default view.
27. Figure 3.27 Perspective selector.
28. Figure 3.28 Naming a target configuration.
29. Figure 3.29 Selecting the appropriate emulator for the target configuration.
30. Figure 3.30 Selecting the appropriate target configuration.
31. Figure 3.31 Selecting the Project Explorer.
32. Figure 3.32 Building a project.
33. Figure 3.33 Building and debugging.
34. Figure 3.34 Changing the configuration option.
35. Figure 3.35 Build types.
36. Figure 3.36 Launching the Debug session.
37. Figure 3.37 Running the project.
38. Figure 3.38 View functions.
39. Figure 3.39 dotp.c: Source code to be completed.
40. Figure 3.40 Clock icon and cycle count.
41. Figure 3.41 Clock setup.
42. Figure 3.42 Clock setup.
43. Figure 3.43 Clock setup.
44. Figure 3.44 Selecting Debug configurations.
45. Figure 3.45 Setting the Debug configuration.
46. Figure 3.46 Setting the device.
47. Figure 3.47 Setting the project location.
48. Figure 3.48 Setting Core 2.
49. Figure 3.49 Setting for the second project.
50. Figure 3.50 Grouping the cores.
51. Figure 3.51 Grouping the cores.
52. Figure 3.52 Console output.
Chapter 04
1. Figure 4.1 N‐bit fractional number representation.
2. Figure 4.2 Binary multiplication of two fractional numbers.
3. Figure 4.3 15‐bit * 15‐bit resulting in Q30 and Q15 formats.
4. Figure 4.4 32‐bit IEEE standard format.
5. Figure 4.5 64‐bit IEEE standard format.
6. Figure 4.6 Accuracy of the 32‐bit floating‐point number.
7. Figure 4.7 Variables before running the code.
8. Figure 4.8 Final results.
Chapter 05
1. Figure 5.1 Optimisation flow procedure.
2. Figure 5.2 Illustration of the different stages of the optimising compiler.
3. Figure 5.3 dotpsa2 file.
4. Figure 5.4 Viewing register pairs.
5. Figure 5.5 Interfacing C and assembly.
6. Figure 5.6 Automatic and manual saving of registers.
7. Figure 5.7 Dependency graph of an FIR filter.
8. Figure 5.8 Dependency graph of an FIR filter.
9. Figure 5.9 Dependency graph of an FIR filter.
10. Figure 5.10 Final dependency graph of an FIR filter.
11. Figure 5.11 DOTP2 instruction.
12. Figure 5.12 Dependency graph of the dotp function using dotp2 instructions.
13. Figure 5.13 dotp function implemented with dotp2 instructions.
14. Figure 5.14 dotp4h instruction functionality.
15. Figure 5.15 Dependency diagram for the dotp function.
16. Figure 5.16 dotp implemented with dotp4h instructions.
17. Figure 5.17 DDOTP4H instruction.
18. Figure 5.18 Dependency diagram for the dotp function using ddotp4h instruction.
19. Figure 5.19 dotp implemented with ddotp4h instructions.
20. Figure 5.20 Illustration of the DDOTP4H instruction.
21. Figure 5.21 Dependency for the DDTOP4h.sa algorithm.
22. Figure 5.22 ddotp4h2.sa.
23. Figure 5.23 TMS320C66x memory banks.
24. Figure 5.24 dotp code to optimise.
25. Figure 5.25 Load balancing by unrolling a loop.
26. Figure 5.26 Loop‐carried dependency graph.
27. Figure 5.27 Loop‐carried dependency graph.
28. Figure 5.28 Console output showing all results.
29. Figure 5.29 Dependency graph.
Chapter 06
1. Figure 6.1 Interrupt response procedure.
2. Figure 6.2 Various interrupts available.
3. Figure 6.3 Interrupts: the big picture.
4. Figure 6.4 CIC controllers for the TMS32C6678 [1].
5. Figure 6.5 CIC controller for the 66AK2H14/12 [2].
6. Figure 6.6 The enabler functionality.
7. Figure 6.7 System Interrupt Status Indexed Set Register (STATUS_SET_INDEX_REG).
8. Figure 6.8 Example of channel mapping.
9. Figure 6.9 Default mapping.
10. Figure 6.10 Host interrupt mapping for the CIC0 viewed with the CCS.
11. Figure 6.11 Host Interrupt Map Registers [3].
12. Figure 6.12 Configuration script.
13. Figure 6.13 Accessing the event combiner.
14. Figure 6.14 Selecting Group 2 to generate Interrupt 6.
15. Figure 6.15 Enabling Events 89 and 90.
16. Figure 6.16 Interrupt controller.
17. Figure 6.17 Event combiner.
18. Figure 6.18 Overall functionality of the interrupt mechanism.
19. Figure 6.19 Experimental setup.
20. Figure 6.20 Console output showing the functions called.
Chapter 07
1. Figure 7.1 TI‐RTOS components.
2. Figure 7.2 TI‐RTOS kernel.
3. Figure 7.3 Various threads available for the TI‐RTOS.
4. Figure 7.4 SYS/BIOS configuration file.
5. Figure 7.5 Hwi module settings.
6. Figure 7.6 Hwi instance settings.
7. Figure 7.7 Configuration script generated.
8. Figure 7.8 Timers events IDs [1].
9. Figure 7.9 Definition of a hook set.
10. Figure 7.10 Definition of a hook set with only two elements.
11. Figure 7.11 Configuration code setting two Hwi hook sets.
12. Figure 7.12 C code defining the hook functions.
13. Figure 7.13 Program counter in main().
14. Figure 7.14 Output showing myRegister1_HWI() and myRegister2_HWI() run before the application reaches main().
15. Figure 7.15 Breakpoint set in myHWI.
16. Figure 7.16 Setting the breakpoint counter to 3.
17. Figure 7.17 Output showing the hook functions running before and after the Hwi.
18. Figure 7.18 A task structure.
19. Figure 7.19 Setting the number of priorities for the tasks.
20. Figure 7.20 Task modes.
21. Figure 7.21 Selecting semaphores for setups.
22. Figure 7.22 Selecting a semaphore module.
23. Figure 7.23 Instance settings.
24. Figure 7.24 TI‐RTOS kernel.
25. Figure 7.25 Adding an event module.
26. Figure 7.26 Event instance settings.
27. Figure 7.27 Event instance settings generated.
28. Figure 7.28 A task synchronised by events.
29. Figure 7.29 Hwi posting two events.
30. Figure 7.30 Example of an external memory fragmentation.
31. Figure 7.31 Setting the HeapMem.
32. Figure 7.32 HeapMem instance settings.
33. Figure 7.33 Code generated from Figure 7.32.
34. Figure 7.34 Setting myHeap section to be in the DDR.
35. Figure 7.35 Setting the default heap.
36. Figure 7.36 HeapBuf with fixed blocks.
37. Figure 7.37 Selecting the HeapBuf for configuration.
38. Figure 7.38 Configuration of the HeapBuf.
39. Figure 7.39 Script obtained from Figure 7.38.
40. Figure 7.40 myHeapSection allocation in DDR3.
41. Figure 7.41 Code generated from Figure 7.40.
42. Figure 7.42 Actual memory allocation.
43. Figure 7.43 Configuration code for testing HeapMultiBuf.
44. Figure 7.44 C code for testing HeapMultiBuf.
45. Figure 7.45 Timing of the clk0Fxn function.
46. Figure 7.46 Console output.
47. Figure 7.47 Output of project.
48. Figure 7.48 Sequence of events required.
49. Figure 7.49 Code to uncomment.
50. Figure 7.50 Select the Swi for configuration.
51. Figure 7.51 Setting of swi0.
52. Figure 7.52 Setting of swi1.
53. Figure 7.53 Setting the configuration for the clock.
54. Figure 7.54 Setting clock0.
55. Figure 7.55 Setting clock1.
56. Figure 7.56 Setting the clock.
57. Figure 7.57 Setting the configuration for the semaphore.
58. Figure 7.58 Adding a semaphore.
59. Figure 7.59 Setting the semaphore.
60. Figure 7.60 Setting the configuration for the tasks.
61. Figure 7.61 Warning that the tasks are not enabled.
62. Figure 7.62 Enabling tasks.
63. Figure 7.63 Adding threads modules.
64. Figure 7.64 Creating task0.
65. Figure 7.65 Creating task1.
66. Figure 7.66 Setting the configuration for the timer.
67. Figure 7.67 Adding a timer instance.
68. Figure 7.68 Configuring the timer.
69. Figure 7.69 Setting the configuration for the Hwi.
70. Figure 7.70 Setting hwi1.
71. Figure 7.71 Console output.
72. Figure 7.72 Console output when both events occur.
73. Figure 7.73 How to post an event.
74. Figure 7.74 Buffer locations.
75. Figure 7.75 Setting a breakpoint and checking the memory allocation.
76. Figure 7.76 Error generated since all memory is in use.
Chapter 08
1. Figure 8.1 TMS320C66AK2H12 functional block diagram.
2. Figure 8.2 TMS32C6678 functional block diagram.
3. Figure 8.3 DMA and QDMA within an EDMA.
4. Figure 8.4 DMA channels for the TMS320C6678.
5. Figure 8.5 IDMA Channel 0 and Channel 1 functions.
6. Figure 8.6 EDMA controller.
7. Figure 8.7 EDMA3 channel controller (EDMA3CC).
8. Figure 8.8 TMS320C6678 EDMA3 events.
9. Figure 8.9 Transfer controllers.
10. Figure 8.10 The four levels of EDMA prioritisation [4].
11. Figure 8.11 Trigger source priority.
12. Figure 8.12 Parameter Ram (PaRam).
13. Figure 8.13 Channel options parameter (OPT).
14. Figure 8.14 Transfer configuration.
15. Figure 8.15 A – Synchronisation.
16. Figure 8.16 AB – Synchronisation.
17. Figure 8.17 Simple EDMA transfer.
18. Figure 8.18 One block transfer.
19. Figure 8.19 Chaining two EDMAs: example.
20. Figure 8.20 Early and normal transfer triggers.
21. Figure 8.21 Linked EDMA (a) before Channel 1 completes the transfer and (b) after Channel 1 completes the transfer.
22. Figure 8.22 Console output showing the OPT fields.
23. Figure 8.23 Console showing the data have been transferred.
24. Figure 8.24 Channel 1 and Channel 2 configurations.
25. Figure 8.25 Console showing initialisation of the source arrays.
26. Figure 8.26 Console showing the data have been transferred.
27. Figure 8.27 Console output showing the OPT fields.
28. Figure 8.28 Console showing the data have been transferred.
Chapter 09
1. Figure 9.1 Shared memory model.
2. Figure 9.2 Example of a message queue mechanism.
3. Figure 9.3 Features for the shared memory and message queue IPCs.
4. Figure 9.4 Modules used by the IPC.
5. Figure 9.5 Components dependency.
6. Figure 9.6 Notify module functionality.
7. Figure 9.7 notify_loopback.c file.
8. Figure 9.8 Output console.
9. Figure 9.9 Example of a MessageQ sender/receiver topology.
10. Figure 9.10 Message priority settings.
11. Figure 9.11 Priority illustration.
12. Figure 9.12 Synchronisation between the writer and the reader.
13. Figure 9.13 Illustration of synchronisation when using Swis.
14. Figure 9.14 How GateMP is used.
15. Figure 9.15 Allocation and using a shared memory.
16. Figure 9.16 Shared memory transport.
17. Figure 9.17 SRIO transport.
18. Figure 9.18 Properties used for the IpcSharedMem project.
19. Figure 9.19 Tools used for the IpcSharedMem project.
20. Figure 9.20 Grouping the cores.
21. Figure 9.21 All cores grouped.
22. Figure 9.22 Output console.
23. Figure 9.23 IPC API references.
24. Figure 9.24 Grouping Core0 and Core1.
25. Figure 9.25 Console output.
26. Figure 9.26 Illustration of the IPC communication using the MessageQ.
27. Figure 9.27 KeyStone II EVM setup.
28. Figure 9.28 Device manager for identifying the COM ports.
29. Figure 9.29 Setting up the COM ports.
30. Figure 9.30 VMware.
31. Figure 9.31 Connecting the flash drive.
32. Figure 9.32 Establishing the connection between the PC and the EVM.
33. Figure 9.33 Edit connections.
34. Figure 9.34 Choose a connection type.
35. Figure 9.35 Select a MAC address and a connection name.
36. Figure 9.36 Select Shared to other computers.
37. Figure 9.37 Output when the connection is made.
38. Figure 9.38 Use ifconfig to check the IP addresses.
39. Figure 9.39 PuTTY terminal after booting.
40. Figure 9.40 Finding the IP address for EVM.
41. Figure 9.41 Setting up FileZilla.
42. Figure 9.42 Importing a file.
43. Figure 9.43 Select Existing Projects into Workspace.
44. Figure 9.44 Selecting the root directory.
45. Figure 9.45 Building a project.
46. Figure 9.46 Console output.
47. Figure 9.47 Importing a Code Composer Studio project.
48. Figure 9.48 Selecting the directory.
49. Figure 9.49 Building a project.
50. Figure 9.50 Console output.
51. Figure 9.51 Transferring the ARM code.
52. Figure 9.52 Transferring the DSP code.
53. Figure 9.53 Transferring the load.sh.
54. Figure 9.54 Changing the permission of a file.
55. Figure 9.55 Console output.
56. Figure 9.56 Accessing files using FileZilla.
57. Figure 9.57 Output after edge detection.
58. Figure 9.58 Console output.
59. Figure 9.59 Output after edge detection.
Chapter 10
1. Figure 10.1 Trace functions available with the standard trace.
2. Figure 10.2 How to select when to start and/or stop tracing.
3. Figure 10.3 Using a function name as the starting location for a capture.
4. Figure 10.4 Trace range specified with a function name and range (32 bytes) for this example.
5. Figure 10.5 Captured data when using Trace in Range.
6. Figure 10.6 Setting the trace variable.
7. Figure 10.7 Trace output after setting the trace variable.
8. Figure 10.8 Store sample configuration.
9. Figure 10.9 Store sample configuration example.
10. Figure 10.10 Event trace with stall.
11. Figure 10.11 Event trace with memory.
12. Figure 10.12 KeyStone CP tracer modules [8].
13. Figure 10.13 Using the CP tracer.
14. Figure 10.14 Debug sub‐system.
15. Figure 10.15 TMS320C66x debug architecture [8].
16. Figure 10.16 Bugged code example that can be detected using state sequencing.
17. Figure 10.17 AET logic.
18. Figure 10.18 System libraries.
19. Figure 10.19 UBM available functions.
20. Figure 10.20 Error generated when asking for more resources.
21. Figure 10.21 UIA components.
22. Figure 10.22 Events functions provided by the UIA.
23. Figure 10.23 Log_Event description [10].
24. Figure 10.24 Multicore Software Development Kit (MCSDK).
25. Figure 10.25 The xdc.runtime package and its modules [12].
26. Figure 10.26 RTOS Analyzer features available.
27. Figure 10.27 System Analyzer additional functions.
28. Figure 10.28 A test code with a main(), a task() and two Swis functions.
29. Figure 10.29 Using SysMin to display System_printf outputs.
30. Figure 10.30 Selecting the task knl to observe the tasks.
31. Figure 10.31 Selecting the Swi knl to observe the Swis.
32. Figure 10.32 RTSC configuration used in this project.
33. Figure 10.33 Test code.
34. Figure 10.34 (a) Opening the UIA dialogue box. (b) Configuring the UIA.
35. Figure 10.35 Available commands used for the RTOS Analyzer.
36. Figure 10.36 Analysis configuration.
37. Figure 10.37 Adding compiler options.
38. Figure 10.38 Output of the logged data.
39. Figure 10.39 Filtering the display message.
40. Figure 10.40 Configuration used in this project.
41. Figure 10.41 Source code for Laboratory experiment 2.
42. Figure 10.42 RTSC configuration used in this project.
43. Figure 10.43 Selecting options for user‐written software.
44. Figure 10.44 Analysis configuration.
45. Figure 10.45 Duration graph showing the time to execute each function (without optimisation).
46. Figure 10.46 Execution graph showing the order in which functions were executed.
47. Figure 10.47 Duration graph showing the time to execute each function (with ‐o3 optimisation).
48. Figure 10.48 Source code.
49. Figure 10.49 Configuration code.
50. Figure 10.50 Using the Main.common$.diags_INFO = Diags.ALWAYS_ON.
51. Figure 10.51 Using the Main.common$.diags_INFO = Diags.ALWAYS_OFF.
52. Figure 10.52 Using the Main.common$.diags_INFO = Diags.RUNTIME_OFF or Main.common$.diags_INFO = Diags.RUNTIME_ON.
53. Figure 10.53 Application code.
54. Figure 10.54 Configuration file.
55. Figure 10.55 Console output showing USER2 and all levels above three.
56. Figure 10.56 Configuration file using USER1 and LEVEL2.
57. Figure 10.57 Output file.
Chapter 11
1. Figure 11.1 Boot address of a CorePac, DSP_BOOT_ADDR, for the KeyStone I.
2. Figure 11.2 Boot address of a CorePac, DSP_BOOT_ADDR, for the KeyStone II.
3. Figure 11.3 High‐level overview of the boot process for the KeyStone I [4].
4. Figure 11.4 High‐level overview of the boot process for the KeyStone II [2].
5. Figure 11.5 Boot mode configuration switches for the TMS320C6678 EVM.
6. Figure 11.6 Boot mode configuration switches for the KeyStone II EVM.
7. Figure 11.7 Boot mode pin for the TMS320C6678 (DEVSTAT) [3].
8. Figure 11.8 Device status register for the TMS320C66AK2H14/12/06 [1].
9. Figure 11.9 Boot mode pins for the TMS320C66AK2H14/12/06 (DEVSTAT) [1].
10. Figure 11.10 DEVSTAT boot mode pins ROM mapping.
11. Figure 11.11 SPI device configuration field descriptions.
12. Figure 11.12 The RBL boot process.
13. Figure 11.13 Detailed RBL boot process for the TMS320C6678.
14. Figure 11.14 The boot table.
15. Figure 11.15 Modifying the boot configuration table.
16. Figure 11.16 Boot complete register, BCx. Note: BCx CorePacx boot status: 0 = CorePacx boot NOT complete, 1 = CorePacx boot complete.
17. Figure 11.17 IBL location. Note: In Rev 1.0 of the C6670 EVM, the FPGA is programmed to invoke the IBL in order to execute the PLL fix, and then jump right back to RBL which continues the process. See the reference for the IBL update [6].
18. Figure 11.18 IBL boot modes.
19. Figure 11.19 IBL configuration.
20. Figure 11.20 TMS320C6678 EVM memory layout.
21. Figure 11.21 File locations.
22. Figure 11.22 Output after running the build.bat file.
23. Figure 11.23 No boot mode switches.
24. Figure 11.24 Loading the GEL file.
25. Figure 11.25 Loading the image.
26. Figure 11.26 Loading the memory.
27. Figure 11.27 Entering the information for the memory block to be loaded.
28. Figure 11.28 Output when the NOR is flashed properly.
29. Figure 11.29 ROM SPI boot mode.
30. Figure 11.30 The boot sequence for the KeyStone II EVM.
31. Figure 11.31 EVM connection to the PC.
32. Figure 11.32 EVMK2H hardware.
33. Figure 11.33 Device manager for identifying the COM ports.
34. Figure 11.34 Setting up the COM ports.
35. Figure 11.35 IP addresses used in this experiment.
36. Figure 11.36 Accessing the network settings.
37. Figure 11.37 Setting the network connection to Bridged.
38. Figure 11.38 Setting the IP address of VMware.
39. Figure 11.39 Setting the host PC IP address.
40. Figure 11.40 Console output after booting Linux.
41. Figure 11.41 Setting eth0’s IP address to 192.168.2.5.
42. Figure 11.42 Accessing the EVM from VMware.
43. Figure 11.43 Using the BMC to verify the EVM boot mode selected.
44. Figure 11.44 Using ipconfig to check the IP addresses.
45. Figure 11.45 Setting the eth0 to IP address 192.168.2.105.
46. Figure 11.46 Monitor showing the file system.
47. Figure 11.47 Host‐mounted NFS server.
48. Figure 11.48 EVM setup.
49. Figure 11.49 Creating directory to hold the TI SDK Linux root file system.
50. Figure 11.50 Check the COM ports.
51. Figure 11.51 Configure the COM ports.
52. Figure 11.52 Power up the EVM and abort the boot.
53. Figure 11.53 Setting the Ubuntu Ethernet connection.
54. Figure 11.54 Restarting the server.
55. Figure 11.55 Booting the EVM.
56. Figure 11.56 EVM booted.
57. Figure 11.57 Finding the EVM IP address.
58. Figure 11.58 Finding the IP address for Ubuntu.
59. Figure 11.59 Connect to the EVM and Ubuntu using FileZilla.
60. Figure 11.60 Creating a directory.
61. Figure 11.61 Terminal showing the created directory test0.
Chapter 12
1. Figure 12.1 The three main components of OpenMP.
2. Figure 12.2 Structure of OpenMP.
3. Figure 12.3 Illustration of forking.
4. Figure 12.4 Output console.
5. Figure 12.5 private() and firstprivate() examples.
6. Figure 12.6 Console output (using private and firstprivate).
7. Figure 12.7 Using reduction.
8. Figure 12.8 Using static scheduling.
9. Figure 12.9 Dynamic scheduling.
10. Figure 12.10 Guided scheduling.
11. Figure 12.11 Output showing the three scheduling kinds (types) with small iteration number.
12. Figure 12.12 Output showing the three scheduling kinds (types) with large iteration number.
13. Figure 12.13 Using omp sections.
14. Figure 12.14 Example with and without task directives.
15. Figure 12.15 Output when using task directive.
16. Figure 12.16 Output when not using task directive.
17. Figure 12.17 Example with OpenMP task.
18. Figure 12.18 Using task and taskwait.
19. Figure 12.19 Output console for four runs.
20. Figure 12.20 Console output.
21. Figure 12.21 Console output.
22. Figure 12.22 Console output.
23. Figure 12.23 Console output.
24. Figure 12.24 Using #pragma omp target.
25. Figure 12.25 Using the map clause.
26. Figure 12.26 Example when data do need to be processed by the host.
27. Figure 12.27 Enabling OpenMP.
28. Figure 12.28 Group the cores before running the code.
29. Figure 12.29 Output console.
30. Figure 12.30 Remove the Auto run option.
31. Figure 12.31 Code using omp section.
32. Figure 12.32 Console outputs.
33. Figure 12.33 EVM connection to the PC.
34. Figure 12.34 Identifying ports used by the EVM.
35. Figure 12.35 Setting up the COM port 14.
36. Figure 12.36 Setting up the COM port 16.
37. Figure 12.37 Evoking the VMware.
38. Figure 12.38 The VMware.
39. Figure 12.39 Edit connections.
40. Figure 12.40 Select an Ethernet connection or add one.
41. Figure 12.41 Create an Ethernet connection.
42. Figure 12.42 Select Ethernet.
43. Figure 12.43 Edit the Connection name.
44. Figure 12.44 Select IPv4 settings.
45. Figure 12.45 Add the Ethernet created.
46. Figure 12.46 KeyStone II EVM booting.
47. Figure 12.47 Login as root.
48. Figure 12.48 Use ifconfig to check the IP addresses.
49. Figure 12.49 Starting FileZilla.
50. Figure 12.50 Using FileZilla to transfer files from the host to the EVM.
51. Figure 12.51 Selecting the files to be transferred to the EVM.
52. Figure 12.52 Changing the file permission.
53. Figure 12.53 Running the dotp project on the EVM.
54. Figure 12.54 Output console showing time consumed when code is running on the target or host.
55. Figure 12.55 Code running on the host.
56. Figure 12.56 OpenMP code.
57. Figure 12.57 The makefile used Makefile.
58. Figure 12.58 Console output showing the results.
Chapter 13
1. Figure 13.1 OpenCL platform model.
2. Figure 13.2 Host, compute devices and compute units.
3. Figure 13.3 Operation of OpenCL.
4. Figure 13.4 Context/platform used in this chapter.
5. Figure 13.5 Example of and application using OpenCL.
6. Figure 13.6 Example 1: Illustration of work item and workgroups.
7. Figure 13.7 Example 2: Illustration of work item and workgroups.
8. Figure 13.8 Example 3: Illustration of work item and workgroups.
9. Figure 13.9 How data are divided amongst work items.
10. Figure 13.10 KeyStone II memory map definition.
11. Figure 13.11 Memory not accessible by the device.
12. Figure 13.12 Data copy when using CL_MEM_USE_HOST_PTR and the data are allocated in the host.
13. Figure 13.13 No data copy when using CL_MEM_USE_HOST_PTR and the data are located by the host in the device memory.
14. Figure 13.14 Using CL_MEM_ALLOC_HOST_PTR.
15. Figure 13.15 Data copy using CL_MEM_COPY_HOST_PTR.
16. Figure 13.16 No barrier is used.
17. Figure 13.17 A barrier is used.
18. Figure 13.18 Hardware setup.
19. Figure 13.19 EVM connection to the PC.
20. Figure 13.20 Device manager for identifying the COM ports.
21. Figure 13.21 Setting up the COM ports.
22. Figure 13.22 VMware start‐up window.
23. Figure 13.23 VMware detected the USB device.
24. Figure 13.24 Edit connections.
25. Figure 13.25 Choose a connection type.
26. Figure 13.26 Select a MAC address and a connection name.
27. Figure 13.27 Select Shared to other computers.
28. Figure 13.28 Output when the connection is made.
29. Figure 13.29 Use ifconfig to check the IP addresses.
30. Figure 13.30 Boot process completed successfully.
31. Figure 13.31 Checking the IP address on the EVM.
32. Figure 13.32 Using FileZilla to transfer files from the host to the EVM.
Chapter 14
1. Figure 14.1 Functional block diagram for the C6678 [1].
2. Figure 14.2 Functional block diagram for the 66AK2H14 [2].
3. Figure 14.3 The Navigator architecture, simplified.
4. Figure 14.4 PKDMA within a peripheral.
5. Figure 14.5 PKDMA transmit side.
6. Figure 14.6 PKDMA receive side.
7. Figure 14.7 Tx Channel N Global Configuration Register A (0x000 + 32 × N) [10].
8. Figure 14.8 Infrastructure PKDMA.
9. Figure 14.9 Host packet descriptor structure: example.
10. Figure 14.10 Host and buffer packets linked.
11. Figure 14.11 Host buffer descriptor structure: example.
12. Figure 14.12 Monolithic descriptor.
13. Figure 14.13 Memory region indexing.
14. Figure 14.14 Configuring the memory region registers.
15. Figure 14.15 The base address of the QMSS configuration registers for the KeyStone I [1].
16. Figure 14.16 The base address of the QMSS configuration registers for the KeyStone II [2].
17. Figure 14.17 Code for reading the number of bytes and the number of descriptors in the queue.
18. Figure 14.18 QMSS architecture (KeyStone I).
19. Figure 14.19 QMSS architecture (KeyStone II).
20. Figure 14.20 Event management with the Navigator.
21. Figure 14.21 Accumulator interrupt generation for the KeyStone I.
22. Figure 14.22 Core‐to‐peripheral movement.
23. Figure 14.23 Core‐to‐core data movement using the Navigator.
Chapter 15
1. Figure 15.1 An arbitrary frequency response of an FIR filter showing the periodicity.
2. Figure 15.2 Filter specifications: (a) ideal, (b) practical.
3. Figure 15.3 Frequency response: (a) desired, (b) ideal.
4. Figure 15.4 Ideal frequency response of a low‐pass filter and (b) its impulse response.
5. Figure 15.5 Frequently used windows.
6. Figure 15.6 MATLAB program for generating the impulse response coefficients.
7. Figure 15.7 Plot of the filter coefficients h(n).
8. Figure 15.8 Transfer function of the designed filter.
9. Figure 15.9 Direct form structure for an FIR filter.
10. Figure 15.10 Impulse response, h(n), for (a) N odd and (b) N even.
11. Figure 15.11 Linear phase structure for (a) N even and (b) N odd.
12. Figure 15.12 Cascade structure.
13. Figure 15.13 PC‐to‐DSP connections.
14. Figure 15.14 USB and UART ports of the EVM.
15. Figure 15.15 C implementation of an FIR filter.
16. Figure 15.16 UART functional block diagram [8].
17. Figure 15.17 Illustration of the synchronisation mechanism.
18. Figure 15.18 FIR filter implementation in C language.
19. Figure 15.19 Java synchronisation code.
20. Figure 15.20 Setting a breakpoint before echoing the character ‘a’.
21. Figure 15.21 Setting the breakpoint property to Refresh All Windows.
22. Figure 15.22 Icon used for displaying the graph properties.
23. Figure 15.23 Graph priority for the input signal (using R_in.graphProp).
24. Figure 15.24 Graph priority for the filtered signal (using R_out.graphProp).
25. Figure 15.25 Java download location (using Windows x64 Offline) [9].
26. Figure 15.26 Importing an Eclipse project.
27. Figure 15.27 Opening an existing Eclipse project.
28. Figure 15.28 Importing a compressed Eclipse project.
29. Figure 15.29 Opening the Java source code.
30. Figure 15.30 Java window for controlling the input signals, the COM ports and the baud rate.
31. Figure 15.31 Default Java application.
32. Figure 15.32 Java application sending data to the UART.
33. Figure 15.33 Code Composer Studio console output.
34. Figure 15.34 Java window message when no data are lost.
35. Figure 15.35 Java output when data are lost.
36. Figure 15.36 Input signal display.
37. Figure 15.37 Filtered signal display.
Chapter 16
1. Figure 16.1 s‐ to z‐plane mapping.
2. Figure 16.2 Relationship between the analogue and digital frequencies.
3. Figure 16.3 Relationship between the analogue and digital frequency responses when using the bilinear transform (BZT).
4. Figure 16.4 Transfer function of an IIR filter designed with the bilinear transform method.
5. Figure 16.5 Direct form I structure.
6. Figure 16.6 Direct form II canonical realisation.
7. Figure 16.7 Alternative to the direct form II realisation.
8. Figure 16.8 Cascade realisation using direct form II.
9. Figure 16.9 Frequency response of a second‐order filter using the impulse invariant method.
10. Figure 16.10 Direct form II structure.
11. Figure 16.11 C code for the implementation of an IIR filter.
12. Figure 16.12 dotp4 with dummy T0 and T00 values.
13. Figure 16.13 Updating d02 and d01.
14. Figure 16.14 C code for the implementation of an IIR filter using SIMD instructions.
15. Figure 16.15 Performance comparison.
16. Figure 16.16 Build options.
17. Figure 16.17 Input signal (Single time −1) and the filtered signal (Single time −0).
Chapter 17
1. Figure 17.1 Basic block diagram of an adaptive filter.
2. Figure 17.2 Steps for implementing an LMS adaptive filter.
3. Figure 17.3 LMS algorithm in C language.
4. Figure 17.4 Coefficients and data storage.
5. Figure 17.5 DSMPY2 operation.
6. Figure 17.6 Illustration of the packh2 instruction.
7. Figure 17.7 Data location before and after the shift.
8. Figure 17.8 Updating data.
9. Figure 17.9 Using the compiler switches to increase the performance.
10. Figure 17.10 Cycles consumed.
11. Figure 17.11 Graph properties settings.
12. Figure 17.12 Output signal for the C code (Single Time ‐1) and (Single Time ‐0) for the linear assembly.
Chapter 18
1. Figure 18.1 Twiddle factors for N = 8.
2. Figure 18.2 Decimation in time (DIT) Radix 2 FFT.
3. Figure 18.3 Bit reversal.
4. Figure 18.4 Decimation in frequency (DIF) Radix 2 FFT.
5. Figure 18.5 Diagram of DIT Radix 2 FFT used for the implementation.
6. Figure 18.6 Flow graph of a butterfly.
7. Figure 18.7 Implementation of the butterfly.
8. Figure 18.8 Main loops for implementing a Radix 2 FFT.
9. Figure 18.9 Tasks to perform.
10. Figure 18.10 General configuration used.
11. Figure 18.11 Real‐Time Software Components (RTSC) tools used.
12. Figure 18.12 Code for generating sinewaves.
13. Figure 18.13 Buffer holding the input data.
14. Figure 18.14 Graph properties used (Display_Time.graphProp).
15. Figure 18.15 Display of the input data.
16. Figure 18.16 Buffer holding the magnitude magg.
17. Figure 18.17 Graph properties.
18. Figure 18.18 FFT display.
19. Figure 18.19 EDMA ping‐pong.
20. Figure 18.20 Properties for displaying the input data in the array magg.
21. Figure 18.21 Display output.
22. Figure 18.22 Properties for displaying the input data in the array magg1.
23. Figure 18.23 FFT magnitude display of data in dstPong.
24. Figure 18.24 Properties for displaying the input data in the array magg2.
25. Figure 18.25 FFT magnitude display of data in dstPing.
Chapter 19
1. Figure 19.1 Cartesian representation of a line.
2. Figure 19.2 (a) Polar and (b) Cartesian coordinates.
3. Figure 19.3 Example of points on a Cartesian representation and their corresponding polar representation.
4. Figure 19.4 Plot of .
5. Figure 19.5 The r function is antisymmetric.
6. Figure 19.6 Diagram showing how to calculate the index z.
7. Figure 19.7 System to implement.
8. Figure 19.8 Generated test image.
9. Figure 19.9 Image property of 1152 × 648.
10. Figure 19.10 MATLAB code for generating the image header file.
11. Figure 19.11 Code for implementing the accumulator.
12. Figure 19.12 Code to extract the maxima of the accumulator.
13. Figure 19.13 Selecting the graphic display.
14. Figure 19.14 Changing, importing or exporting the properties of a graph.
15. Figure 19.15 Properties for the input image (in): Image_in_properties.txt.
16. Figure 19.16 Input image (in): Image_in_properties.txt.
17. Figure 19.17 Properties for the image after the edge detection (out): Image_out_properties.txt.
18. Figure 19.18 Image output after edge detection: Image_out_properties.txt.
19. Figure 19.19 Image properties for the accumulator: accumulator_properties.txt.
20. Figure 19.20 Section of the accumulator output: accumulator_properties.txt.
21. Figure 19.21 Values and coordinates of the five maxima.
Chapter 20
1. Figure 20.1 Computation of depth.
2. Figure 20.2 Reducing the ROI.
3. Figure 20.3 (a) Left image, (b) right image and (c) left and right images merged showing the disparities reduced.
4. Figure 20.4 Reduced disparity, line by line.
5. Figure 20.5 Estimation of disparity range from neighbouring pixels [7].
6. Figure 20.6 Corresponding pixels appear at different coordinates on the left and the right images.
7. Figure 20.7 Indices calculation.
8. Figure 20.8 Selecting the image display feature.
9. Figure 20.9 SAD implementation in C language.
10. Figure 20.10 SAD output image.
11. Figure 20.11 NCC implementation in C language.
12. Figure 20.12 NCC output image.
13. Figure 20.13 ZNCC implemented in C language.
14. Figure 20.14 ZNCC output image.
15. Figure 20.15 Time comparison between SAD, NCC and ZNCC with no optimisation.
16. Figure 20.16 Time comparison between SAD, NCC and ZNCC with optimisation (−O3).

From Algorithms to Real‐time Implementation on the TMS320C66x SoC