We are living in an era of supercomputing where smartphones, smartwatches, and smart technology have become an inevitable part of our daily life. The research and development in the field of transistors, which forms the basic building block of the computing devices, has driven this “smart” revolution. The dimensions of the transistors have been incessantly scaled down to increase the number of transistors per chip, which has not only reduced the chip area enabling hand-held devices but also increased the functionality and operating frequency and decreased the power dissipation. However, all the modern-day transistors such as metal-oxide-semiconductor field-effect transistors (MOSFETs) (or tunnel field-effect transistors or ferroelectric field-effect transistors, etc.) contain two metallurgical junctions: one at the source–channel interface and other at the channel–drain interface. To further scale down the modern transistors to the sub-10 nm regime and exploit the performance improvements brought by the scaling process, the doping must change abruptly from a high value (typically ∼10²⁰ cm^–3) in the source and drain regions to a low value (typically ∼10¹⁴–10¹⁶ cm⁻³) with complementary dopants in the channel region within a span of a few nanometers (∼1–2 nm). Experimental realization of such an ultrasteep doping profile is extremely difficult even with the industry-standard ion-implantation process. To add to this misery, achieving high dopant activation in the heavily doped source/drain regions requires a high-temperature annealing. The annealing process, in turn, leads to a thermally assisted lateral diffusion of dopant atoms from source/drain regions into the channel region. This further restricts the possibility of realizing ultrasteep doping profiles in MOSFETs. As lateral diffusion is inevitable while annealing, the simultaneous requirement of a high dopant activation and an ultrasteep doping profile puts a complex constraint on the thermal budget. Our lives as device designers would have been much easier if there have been no metallurgical junctions. Therefore, to alleviate the need for ultrasteep doping profiles, field-effect transistors without any metallurgical junction were proposed to facilitate the scaling down of the conventional MOSFETs. These junctionless FETs (JLFETs) utilize an ultrathin semiconductor film with a gate stack to control its resistance and modulate the current flowing through it. The absence of a metallurgical junction leads to an altogether new conduction mechanism and device properties, which are different from conventional MOSFETs.

Surprisingly, the working principle of the JLFET was conceptualized and patented by Austrian-Hungarian physicist Julius Edgar Lilienfield in 1930 even before the discovery of the point-contact transistor by Shockley, Brattain, and Bardein in 1947. But it was only with the recent advancements in the fabrication technology that nanowire JLFETs were experimentally realized in 2010, inspired by Lilienfield's work. An exhaustive research has been carried out on JLFETs since then. The number of research papers on JLFETs has increased exponentially, and our understanding of JLFETs has also improved significantly over the years. The junctionless architecture, owing to its low cost, low fabrication complexity, and lower thermal budget, has opened up a new domain of exciting possibilities whereby JLFETs could be employed as sensors, memories, such as capacitor-less DRAM, NAND flash memory, display devices, and for biocompatible, optoelectronic, and three-dimensional (3D) sequential integrated circuit applications apart from logic applications. The enormous possibilities offered by the junctionless transistor architecture are exciting opportunities to the researchers to explore and invent novel device structures for a variety of applications ranging from logic circuits to memories, sensors, 3D integration, and display technology. However, due to the lack of a comprehensive textbook, research papers are currently the primary source of knowledge on JLFETs. With a plethora of research papers appearing on JLFETs, gaining a basic understanding of a JLFET and keeping track of the latest research is a challenge.

This book endeavors to be a comprehensive guide for those who are about to begin their study (and research) or have already started working on JLFETs. It provides a one-stop volume for studying JLFETs for someone having a basic knowledge of device physics. The book covers the fundamental physics behind the operation of JLFETs and provides a comparative analysis of different performance metrics of the JLFETs with respect to the MOSFETs. The book unfolds the challenges for JLFETs if they were to replace MOSFETs and incorporates a comprehensive study of the device architectures and designs proposed in the literature to mitigate the challenges and improve the performance of JLFETs. The book also includes a detailed analysis of the junctionless devices realized without the need for conventional chemical doping. In addition, it discusses in detail the different approaches used for analytical or compact modeling of JLFETs for the purpose of circuit design and circuit simulation. Therefore, this book is the first attempt to encompass the research reported on JLFETs on aspects spanning from device architectures and simulations to analytical modeling. Also, every aspect of the JLFET has been compared to the MOSFET so that the material presented in the book allows the entire semiconductor device fraternity to evaluate the potential of JLFETs and take informed decisions regarding its integration with the prevailing technology in the industry. Another unique feature of this book is that it describes the process of carrying out numerical simulations of JLFETs using the technology computer-aided design (TCAD) tool Sentaurus S-device. TCAD simulations are helpful for studying the behavior of any semiconductor device without getting into the complex process of fabrication and characterization, thus reducing the time to market. The calibrated simulation setup provided in the book would definitely aid the researchers especially the beginners in the field and provide them with an effective tool to analyze, evaluate, and invent new junctionless architectures for different applications, which may serve as a stepping-stone in the early stage of their work. We hope that this book covering the fundamentals of the JLFET along with their analytical modeling and simulation using TCAD would encourage the beginners to pursue research on JLFETs and augment the efforts of the existing researchers to realize a power-efficient JLFET for “green” electronics, which would eventually lead to a better society.