Table of Contents
Cover
Preface
List of Contributors
Acknowledgments
1 History of Embedded and Fan‐Out Packaging Technology
1.1 Introduction
1.2 First Embedding Technologies Based on MCM‐D Concepts
1.3 First Embedding Technologies Based on Organic Laminates and Flex
1.4 Helsinki University of Technology and Imbera Electronics Embedded Chips
1.5 Fraunhofer IZM/TU Berlin Chip‐in‐Polymer (CiP)
1.6 HiCoFlex, Chip‐in‐Flex, and UTCP
1.7 Conclusion
References
2 FO‐WLP Market and Technology Trends
2.1 Introduction
2.2 FO‐WLP: A Disruptive Technology
2.3 Embedded Die Packaging
2.4 FO‐WLP Advantages
2.5 FO‐WLP Versions
2.6 Challenges for FO‐WLP
2.7 Drivers for FO‐WLP
2.8 Strong Demand for FO‐WLP
References
3 Embedded Wafer‐Level Ball Grid Array (eWLB) Packaging Technology Platform
3.1 Technology Description
3.2 Basic Package Construction
3.3 Manufacturing Process Flow and BOM
3.4 System Integration Capability
3.5 Manufacturing Format and Scalability
3.6 Package Performance
3.7 Robustness and Reliability Data
3.8 Electrical Test Considerations
3.9 Applications and Markets
References
4 Ultrathin 3D FO‐WLP eWLB‐PoP (Embedded Wafer‐Level Ball Grid Array‐Package‐on‐Package) Technology
4.1 Introduction
4.2 eWLB‐MLP (Mold Laser Package‐on‐Package) Technology
4.3 3D eWLB‐PoP Technology
4.4 3D eWLB SiP/Module
4.5 Conclusions
References
5 NEPES’ Fan‐Out Packaging Technology from Single die, SiP to Panel‐Level Packaging
5.1 Introduction
5.2 Structure and Process Flow
5.3 Thin Fan‐Out Packaging
5.4 Double‐Sided Fan‐Out Packaging
5.5 Via Frame (VF) Fan‐Out Package
5.6 System‐in‐Package
5.7 Panel‐Level Package
5.8 Performance and Reliability
5.9 Application
5.10 Roadmap and Remarks
References
6 M‐Series™ Fan‐Out with Adaptive Patterning™
6.1 Technology Description
6.2 Basic Package Construction
6.3 Manufacturing Process Flow and BOM
6.4 Design Features and System Integration Capability
6.5 Adaptive Patterning
6.6 Manufacturing Format and Scalability
6.7 Robustness and Reliability Data
6.8 Electrical Test Considerations
6.9 Applications and Markets
Acknowledgment
References
7 SWIFT® Semiconductor Packaging Technology
7.1 Technology Description
7.2 Basic Package Construction
7.3 Manufacturing Process
7.4 Design Features
7.5 Manufacturing Format and Scalability
7.6 Package Performance
7.7 Thermal Performance
7.8 Robustness and Reliability Data
7.9 Applications and Markets
References
8 Embedded Silicon Fan‐Out (eSiFO®) Technology for Wafer‐Level System Integration
8.1 Technology Description
8.2 Basic Package Construction
8.3 Manufacturing Process Flow
8.4 Design Features
8.5 System Integration Capability
8.6 Manufacturing Format and Scalability
8.7 Package Performance
8.8 Robustness and Reliability Data
8.9 Applications and Markets
Acknowledgment
References
9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i
2
Board Technology
9.1 Technology Description
9.2 Basic Interposer Construction
9.3 Manufacturing Process Flow and BOM
9.4 Design Features
9.5 System Integration Capability
9.6 Manufacturing Format and Scalability
9.7 Package Performance
9.8 Robustness and Reliability Data
9.9 Electrical Test Considerations
9.10 Applications and Markets
9.11 Summary
References
10 Embedding of Power Electronic Components: The Smart p
2
Pack Technology
10.1 Introduction
10.2 Technology Description p Pack
10.3 Basic Package Construction
10.4 The p Pack Technology Process Flow
10.5 Smart p Pack
10.6 Package Performance
10.7 Applications and Markets
10.8 Summary
Acknowledgments
References
11 Embedded Die in Substrate (Panel‐Level) Packaging Technology
11.1 Technology Description
11.2 Basic Package Construction
11.3 Manufacturing Process Flow and BOM
11.4 Design Features
11.5 System Integration Capability
11.6 Package Performance
11.7 Diversity of EDS Technology: Module
11.8 Diversity of EDS Technology: Power Devices
11.9 Applications and Markets
References
12 Blade: A Chip‐First Embedded Technology for Power Packaging
12.1 Technology Description
12.2 Development and Implementation
12.3 Basic Package Construction
12.4 Manufacturing Process Flow and BOM
12.5 Design Features
12.6 System Integration Capability
12.7 Manufacturing Format and Scalability
12.8 Package Performance
12.9 Robustness and Reliability Data
12.10 Electrical Test Considerations
12.11 Applications and Markets
Acknowledgments
References
13 The Role of Liquid Molding Compounds in the Success of Fan‐Out Wafer‐Level Packaging Technology
13.1 Introduction
13.2 The Necessity of Liquid Molding Compound for FO‐WLP
13.3 The Required Parameters of Liquid Molding Compound for FO‐WLP
13.4 Design of LMC Resin Formulation
13.5 Development of LMC in Connection with Latest Requirements
13.6 Current LMC Representative Proprieties
13.7 Conclusions
Acknowledgment
References
14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan‐Out Wafer‐Level Packaging (FO‐WLP)
14.1 Introduction
14.2 Brief History of PI/PBO‐Based Materials in Semiconductor Applications
14.3 Dielectric Challenges in FO‐WLP Applications
14.4 HDM Material Sets for FO‐WLP
14.5 PBO‐Gen3 (Positive‐Acting, Aqueous‐Developable Material)
14.6 PBO‐Gen3 Process Flow
14.7 PBO‐Gen3 Lithography
14.8 PBO‐Gen3 Material Properties
14.9 PBO‐Gen3 Dielectric Reliability Testing
14.10 PBO‐Gen3 Package Reliability Performance (TCT Testing at Component and Board Level)
14.11 Performance Comparison Between PBO‐Gen3 and PBO‐Gen2
14.12 PI‐Gen2 (Negative‐Acting, Solvent‐Developable Material)
14.13 PI‐Gen2 Process Flow
14.14 PI‐Gen2 Lithography
14.15 PI‐Gen2 Material Properties
14.16 PI‐Gen2 Dielectric Reliability Data
14.17 PI‐Gen2 Package Reliability Performance (Component and Board Level)
14.18 Comparison Between PBO‐Gen3 and PI‐Gen2
14.19 Summary
References
15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer‐Level Packaging
15.1 Description of Technology
15.2 Material Challenges for FO‐WLP
15.3 Material Overview
15.4 Process Flow
15.5 Material Properties
15.6 Design Rules
15.7 Reliability
15.8 Next Steps
References
16 The Role of Pick and Place in Fan‐Out Wafer‐Level Packaging
16.1 Introduction
16.2 Equipment Requirements for Fan‐Out Bonders
16.3 Avoiding Fan‐Out Bonding Pitfalls
16.4 Equipment Qualification for Fan‐Out Pick and Place
16.5 Running a Large Area Glass‐on‐Glass Process
16.6 Running a Glass‐on‐Carrier Process
16.7 Running a Reference Production Lot with Test Die
16.8 Conclusions
References
17 Process and Equipment for eWLB: Chip Embedding by Molding
17.1 Introduction
17.2 Historical Background Molding
17.3 The Molded Wafer Idea: Key for the Fan‐Out eWLB Technology
17.4 The Compression Molding Process
17.5 Principle Challenges for Chip Embedding with Compression Molding
17.6 Process Development Solutions for Principle Challenges
17.7 Compression Molding Equipment for Chip Embedding
17.8 Chip Embedding Features Achieved by Compression Molding
17.9 Conclusions and Next Steps
Acknowledgments
References
18 Tools for Fan‐Out Wafer‐Level Package Processing
18.1 Turnkey Solution for Fan‐Out Wafer‐Level Packaging
18.2 Die Placement Process and Tools for FO‐WLP
18.3 Encapsulation Tool for Large Format Encapsulation
18.4 The Test Handling and Packing Solution for Wafer‐Level Packaging and FO‐WLP
References
19 Equipment and Process for eWLB: Required PVD/Sputter Solutions
19.1 Background
19.2 Process Flow
19.3 Equipment Challenges for FO‐WLP
19.4 Equipment Developed to Overcome Challenges
19.5 Additional Equipment Features
19.6 Design Rules Related to the Equipment
19.7 Reliability
19.8 Next Steps
References
20 Excimer Laser Ablation for the Patterning of Ultra‐fine Routings
20.1 Advanced Packaging Applications and Technology Trends
20.2 The High Density Structuring Challenge
20.3 Excimer Laser Ablation Technology
20.4 Summary and Conclusion
References
21 Temporary Carrier Technologies for eWLB and RDL‐First Fan‐Out Wafer‐Level Packages
21.1 Slide‐Off Debonding for FO‐WLP
21.2 Laser Debonding: Universal Carrier Release Process for Fan‐Out Wafer Packages
21.3 Parameters Influencing DPSS Laser Debonding
Acknowledgments
References
22 Encapsulated Wafer‐Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection
22.1 Improving the Conventional WLCSP Structure
22.2 The Encapsulated WLCSP Process
22.3 Advantages of the Encapsulated WLCSP, eWLCSP
22.4 eWLCSP Reliability
22.5 Reliability of Larger eWLCSP over 6 mm × 6 mm Package Size
22.6 eWLCSP Wafer‐Level Final Test
22.7 Conclusions
References
23 Embedded Multi‐die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect
23.1 Introduction
23.2 EMIB Architecture
23.3 High Level EMIB Process Flow
23.4 EMIB Signaling
23.5 Conclusions
Acknowledgments
References
24 Interconnection Technology Innovations in2.5D Integrated Electronic Systems
24.1 Introduction
24.2 Polymer‐Enhanced TSVs
24.3 HIST
24.4 Conclusion
References
Index
End User License Agreement
List of Tables
Chapter 2
Table 2.1 Companies offering FO‐WLP.
Table 2.2 Fan‐out WLP examples.
Chapter 3
Table 3.1 Formats and area scaling factors for different substrate formats....
Table 3.2 Overview consumer reliability performance of FO‐WLP.
Table 3.3 Overview automotive reliability performance of FO‐WLP.
Chapter 4
Table 4.1 Value proposition of eWLB‐MLP.
Table 4.2 eWLB‐MLP test vehicles specification.
Table 4.3 Package‐level reliability results of eWLB‐MLP packages.
Table 4.4 Value proposition of eWLB‐PoP.
Table 4.5 eWLB‐PoP test vehicles (TV) specifications.
Table 4.6 Package‐level reliability results of 3D eWLB‐PoP.
Table 4.7 Electrical parasitic values of
R
,
L
of eWLB‐PoP and fcPoP at 1 GHz....
Table 4.8 Board‐level reliability test results of 3D eWLB‐PoP.
Chapter 5
Table 5.1 The package‐level reliability of FO‐WLP with double‐sided RDL.
Table 5.2 Package structure details of FOWL‐SiP and package reliability test ...
Chapter 6
Table 6.1 M‐Series design rules.
Table 6.2 M‐Series reliability results.
Chapter 7
Table 7.1 SWIFT vs. FO‐WLP process.
Table 7.2 SWIFT technology roadmap.
Table 7.3 Comparison of fan‐out signal integrity at 4 Gbps.
Table 7.4 Comparison of fan‐in signal integrity at 4 Gbps.
Table 7.5 Comparison of fan‐out signal integrity at 6 Gbps.
Table 7.6 Comparison of fan‐in signal integrity at 6 Gbps.
Table 7.7 Comparison of signal integrity at 28 Gbps.
Table 7.8 Time for die temperature to reach 105 °C (9 W power dissipation).
Table 7.9 Drop test results.
Chapter 8
Table 8.1 Design rules for the eSiFO package.
Table 8.2 Technology development roadmap for the eSiFO package.
Table 8.3 Electrical test results.
Table 8.4 Package‐level reliability test results.
Chapter 9
Table 9.1 Reliability test data.
Table 9.2 Significant terms for DOE.
Chapter 12
Table 12.1 Data sheet values of thermal resistances to package top and to pac...
Table 12.2 Blade solder joint robustness in TCoB test.
Chapter 13
Table 13.1 Standard LMC properties.
Chapter 14
Table 14.1 PI and PBO dielectric challenges for FO‐WLP applications.
Table 14.2 Overview of PI/PBO material sets.
Table 14.3 PBO‐Gen3 process flow.
Table 14.4 Film retention (FR) comparison between PBO‐Gen3 and PBO‐Gen2.
Table 14.5 PBO‐Gen3 (high viscosity version) process flow for thick film form...
Table 14.6 PBO‐Gen3 and PBO‐Gen2 thick film patterning capability.
Table 14.7 PBO‐Gen3 and PBO‐Gen2 cured film properties.
Table 14.8 Mechanical properties after TCT (−65 °C/15 min to 150 °C/15 min). ...
Table 14.9 Mechanical properties (ambient versus −50 °C).
Table 14.10 Mechanical properties after PCT (121 °C/100% RH, 168 h).
Table 14.11 Chemical resistance of PBO‐Gen2 and PBO‐Gen3.
Table 14.12 Specification of FO‐WLP test vehicle.
Table 14.13 PBO‐Gen3 (cured 200 °C/2 h) reliability test results after TCT at...
Table 14.14 Reliability test results comparing PBO‐Gen3 with PBO‐Gen2.
Table 14.15 PI‐Gen2 process flow.
Table 14.16 PI‐Gen1 and PI‐Gen2 film thickness and % FR variation during proc...
Table 14.17 PI‐Gen2 cured film properties.
Table 14.18 PI‐Gen2 mechanical properties measured at low temperature (−50 °C...
Table 14.19 PI‐Gen2 mechanical properties after PCT.
Table 14.20 PI‐Gen2 chemical resistance.
Table 14.21 PI‐Gen2 reliability test results after TCT at component and board...
Table 14.22 Comparison between PBO‐Gen3 and PI‐Gen2.
Chapter 15
Table 15.1 Overview of the key material properties of typical photosensitive ...
Table 15.2 Material requirements comparison between “chip‐first” and “chip‐la...
Table 15.3 Overview of the main characteristics of thermoplastic and thermose...
Table 15.4 Material properties overview of various dielectric materials for F...
Table 15.5 Details of both test vehicles TV A and TV B used for reliability c...
Chapter 16
Table 16.1 List of different fan‐out and embedded wafer‐ and panel‐level pack...
Chapter 18
Table 18.1 Comparison of compression system from three manufacturers.
Chapter 21
Table 21.1 Mechanical properties of carrier materials for temporary bonding in F...
Table 21.2 Comparison of UV laser sources for debonding in terms of their respec...
Chapter 22
Table 22.1 Layer thicknesses.
Table 22.2 Component‐level reliability test results of eWLCSP.
Table 22.3 TCoB reliability test results for eWLCSP.
Table 22.4 Drop test results for eWLCSP.
Table 22.5 eWLCSP test vehicle (TV) details.
Table 22.6 Component‐level reliability results.
Table 22.7 Board‐level reliability test results.
Table 22.8 Visual inspection results after auto handler socket insertion test...
Chapter 23
Table 23.1 Key attributes of the silicon bridge.
Chapter 24
Table 24.1 Comparison of polymer‐embedded vias and polymer‐clad TSVs with other ...
Table 24.2 Comparison of the demonstrated coaxial vias to other coaxial TSV tech...
List of Illustrations
Chapter 1
Figure 1.1 Schematic of an embedded MCM proposed by Johnson et al. [3].
Figure 1.2 Pictures from US Patent no. 3,579,056.
Figure 1.3 Principle of the GE HDI embedding technology.
Figure 1.4 GE HDI embedding process flow [8].
Figure 1.5 GE plastic encapsulated HDI process flow.
Figure 1.6 Process steps of the embedding process: laser cutting of the ceram...
Figure 1.7 Embedded SRAM in AlN (SEM) and with the first photosensitive BCB a...
Figure 1.8 Multilayer metallization (Cu/BCB) over the SRAM (video print). Met...
Figure 1.9 Small die with fan‐out BGA pitch of 0.5 mm (left) and large die em...
Figure 1.10 Crosscut of fan‐out embedding die with a completely encapsulated ...
Figure 1.11 Vertical interconnect element (VIE) (manufacturing, sawing, 90° t...
Figure 1.12 Schematic of the 3D concept of the embedding technology and view ...
Figure 1.13 Process flow of the planar embedding technology for power modules...
Figure 1.14 Thermal test of MCM with a size of 2 in. × 2 in. with six embedde...
Figure 1.15 Simplified schematic of the embedding of an Si RF power module.
Figure 1.16 Video print of the topside of the embedded components and after m...
Figure 1.17 Crosscut through the embedded module with the multilayer wiring: ...
Figure 1.18 Principle of TCI.
Figure 1.19 TCI test vehicle after flip‐chip attach on wafer level and crossc...
Figure 1.20 TCI for MEMS: RDL on the embedded ASIC, fully processed SiPs, cro...
Figure 1.21 Embedded LED: cross section, complete module on AlN substrate and...
Figure 1.22 Principle and example of the NEO‐wafer concept from Irvine Sensor...
Figure 1.23 3D stacking using the NEO‐wafer principle.
Figure 1.24 First part of the process flow of the Wirefree Die‐on‐Die (WDoD) ...
Figure 1.25 Second part of the process flow of the Wirefree Die‐on‐Die (WDoD)...
Figure 1.26 Process flow of EWLP.
Figure 1.27 Example of a 24 in. × 18 in. fully populated molded panel with em...
Figure 1.28 Process flow of the panel‐level molding process using granular mo...
Figure 1.29 Principle of the Chip‐on‐Flex concept.
Figure 1.30 GE Chip‐on‐Flex process flow.
Figure 1.31 GE HDI technology: 100 W point of load power converter module.
Figure 1.32 Imbera process flow for IMB.
Figure 1.33 Cross section of embedded die using the Imbera process.
Figure 1.34 Process flow of the modified IMB process.
Figure 1.35 Interconnect principle of an embedded chip in a PCB buildup layer...
Figure 1.36 Process steps of chip embedding: (a) die bonding, (b) embedding i...
Figure 1.37 Cross section of a micro‐via interconnect to an embedded chip and...
Figure 1.38 Cross section of the micro camera module with image sensor on top...
Figure 1.39 Process flow of the HiCoFlex process.
Figure 1.40 Process flow of the Chip‐in‐Flex technology.
Figure 1.41 Overview of the process flow of the UTCP.
Figure 1.42 Cost advantage of die splitting for increasing die area and for d...
Chapter 2
Figure 2.1 (a) Active die face‐down FO‐WLP die placement. (b) Active die face...
Figure 2.2 NXP’s RCP FO‐WLP process flow.
Figure 2.3 Face‐up FO‐WLP process flow.
Figure 2.4 Deca’s M‐Series® face‐up FO‐WLP process flow.
Figure 2.5 Deca’s adaptive patterning process.
Figure 2.6 Amkor’s SWIFT package structure proposals.
Figure 2.7 JCAP’s ECP package and structure proposal.
Figure 2.8 Huatian’s eSiFO package and structure proposal.
Figure 2.9 Qualcomm’s FO‐WLP in production. (a) Audio codec 4.25 mm × 3.90 mm...
Figure 2.10 TSMC’s InFO‐PoP technology used in Apple’s A10 process for the iP...
Figure 2.11 ASE FOCoS process.
Figure 2.12 Forecasted growth of FO‐WLP.
Chapter 3
Figure 3.1 Principle of WLP with and without redistribution layer (RDL).
Figure 3.2 RDL stack with UBM for WLP.
Figure 3.3 Driving factors for FO‐WLP development.
Figure 3.4 X‐GOLD 616 baseband product in eWLB package technology.
Figure 3.5 Basic construction of FO‐WLP.
Figure 3.6 Comparison between FC‐CSP and FO‐WLP (example: eWLB).
Figure 3.7 Product package position for WLP and FC‐CSP [1].
Figure 3.8 Reconstitution of artificial wafer [2].
Figure 3.9 eWLB cross section and process overview [2].
Figure 3.10 Cross section of eWLB.
Figure 3.11 Side‐by‐side approach of FO‐WLP.
Figure 3.12 Side‐by‐side approach of SWIFT [3].
Figure 3.13 Heterogeneous system integration [3].
Figure 3.14 Heterogeneous system integration of ASIC and MEMS.
Figure 3.15 Electrical performance comparison (resistance, inductance) [5].
Figure 3.16 Thermal performance comparison.
Figure 3.17 eWLB 77 GHz radar package.
Figure 3.18 Electrical testing flows for (1) CSP and (2) and (3) for FO‐WLP. ...
Chapter 4
Figure 4.1 (a) 300 mm eWLB carrier and eWLB packages and (b) evolution of eWL...
Figure 4.2 The eWLB assembly process flow.
Figure 4.3 Schematics of package structure of eWLB‐MLP. (a) eWLB‐MLP bottom p...
Figure 4.4 Micrograph of eWLB‐MLPs: (a) TV1 and (b) TV2.
Figure 4.5 Assembly process flow of eWLB‐MLP.
Figure 4.6 Micrograph of top view of eWLB‐MLP, after laser ablation process t...
Figure 4.7 SEM micrograph of a cross‐sectional view of eWLB‐MLP, after solder...
Figure 4.8 Board‐level reliability test samples of eWLB‐MLP mounted on PCB.
Figure 4.9 SEM micrographs of eWLB after stacking 500 μm high eWLB top packag...
Figure 4.10 Weibull plot of TCoB reliability of 10 mm × 10 mm eWLB‐MLP (−40/1...
Figure 4.11 Weibull plot of drop reliability of 10 mm × 10 mm eWLB‐MLP.
Figure 4.12 SEM micrographs of failure analysis of eWLB‐MLP board‐level relia...
Figure 4.13 (a) Schematics of package structure of 3D ultrathin eWLB‐PoP bott...
Figure 4.14 Micrograph of 3D eWLB‐PoP: (a) TV1 and (b) TV2.
Figure 4.15 Experimental thermal characterization data for 3D eWLB‐PoP with d...
Figure 4.16 Micrographs of a cross section of a 3D eWLB‐PoP stacked after top...
Figure 4.17 Schematics of 3D eWLB SiP (a) with interposer and (b) discretes o...
Figure 4.18 Micrographs of 3D eWLB SiP with interposer.
Figure 4.19 Micrographs of a 3D SiP eWLB‐PoP with discretes on an interposer ...
Chapter 5
Figure 5.1 Fan‐out wafer‐level packaging process flow.
Figure 5.2 Schematic and picture of FO‐WLP.
Figure 5.3 An example of EGP and design for signals and grounds.
Figure 5.4 Thin profile FO‐WLP (two die, PoP supportive).
Figure 5.5 FO‐WLP with double‐sided RDL.
Figure 5.6 Typical structure of VF‐FOP.
Figure 5.7 Process flow of VF‐FOP.
Figure 5.8 Example of VF‐FOP application to various package type. (a) Single‐...
Figure 5.9 Process images of FOWL‐SiP.
Figure 5.10 Image of an actual module product built with FO‐WLP technology.
Figure 5.11 Inductor on multi‐die fan‐out WLP with multi‐RDL.
Figure 5.12 Fan‐out WLP and panel‐level package.
Figure 5.13 Thermal simulation of fan‐out WLP on the effect of EGP.
Figure 5.14 Comparison of thermal performance between no EGP (type 1) and EGP...
Figure 5.15 Radar sensor fan‐out package designed for automotive application....
Figure 5.16 Insertion loss test result at various temperatures.
Figure 5.17 Insertion loss test result at 77 GHz.
Figure 5.18 The FO‐WLP types and application products produced by nepes Corpo...
Figure 5.19 Via frame FO‐WLP for fingerprint sensor device application.
Figure 5.20 Via frame FO‐WLP for optical module.
Figure 5.21 Package structure of DotDuino and comparison with Arduino board....
Figure 5.22 Application of FOWL‐SiP in IoT module.
Figure 5.23 FO‐WLP lineup and roadmap.
Chapter 6
Figure 6.1 (a) Schematic of M‐Series FO‐WLP. (b) Actual cross section of M‐Se...
Figure 6.2 BLR comparison of M‐Series versus WLCSP.
Figure 6.3 Adaptive patterning methodology using adaptive routing.
Figure 6.4 Basic package construction of M‐Series.
Figure 6.5 Conventional fan‐out structure with electrical shorting failure....
Figure 6.6 Nonplanarity of silicon to EMC surface in conventional fan‐out. ...
Figure 6.7 Planar surface over silicon device to EMC interface on M‐Series.
Figure 6.8 M‐Series process flow for a fully molded FO‐WLP.
Figure 6.9 Standard M‐Series cross‐sectional stack‐ups.
Figure 6.10 M‐Series buildup with staggered vias.
Figure 6.11 M‐Series buildup with UBM and BGA ball directly over a Cu stud.
Figure 6.12 M‐Series buildup with UBM via in RDL2 via.
Figure 6.13 M‐Series buildup with fully stacked vias.
Figure 6.14 M‐Series BGA view showing BGA balls over die shadow shown as blac...
Figure 6.15 M‐Series BGA view showing BGA balls over die shadow in light.
Figure 6.16 M‐Series peripheral PoP schematic.
Figure 6.17 M‐Series fan‐in PoP schematic.
Figure 6.18 Illustration of die shift from pick and place tolerances and mold...
Figure 6.19 The generation of unique per‐package lithography patterns by adap...
Figure 6.20 For adaptive alignment, the PRDL‐UBV interface must be designed w...
Figure 6.21 Adaptive via truncation maximizes UBV area with minimal changes t...
Figure 6.22 Adaptive routing combines the die‐aligned and package‐aligned pre...
Figure 6.23 Adaptive alignment can be combined with adaptive routing for mult...
Figure 6.24 Similarities of solar cell wafer process versus Deca’s WLCSP proc...
Figure 6.25 The 600 mm × 600 mm panel configured for quartering to 300 mm squ...
Figure 6.26 M‐Series manufacturing formats.
Figure 6.27 300 mm round to 600 mm by 600 mm square panel.
Chapter 7
Figure 7.1 Traditional PoP structures. (a) Exposed‐die TMV PoP. (b) Interpose...
Figure 7.2 SWIFT PoP structure. (Note: Copper pillars on left and right sides...
Figure 7.3 SWIFT process flow.
Figure 7.4 Package height comparison with cross‐sectional view of an FC‐PoP a...
Figure 7.5 Key enabling chip‐last HD‐FO technologies.
Figure 7.6 Chip‐last HD‐FO package with tall Cu pillars and top RDL.
Figure 7.7 SWIFT package roadmap.
Figure 7.8 Representative cross section of embedded WL‐SiP.
Figure 7.9 SEM photo of shielding Cu trace interface. (Note: the Cu RDL trace...
Figure 7.10 SWIFT on substrate package with deconstructed logic.
Figure 7.11 Cross section of four test packages.
Figure 7.12 Comparison of eye diagrams at 4 Gbps.
Figure 7.13 Comparison of eye diagrams at 6 Gbps.
Figure 7.14 Return loss comparison.
Figure 7.16 Cross‐talk comparison.
Figure 7.17 Comparison of eye diagrams at 28 Gbps.
Figure 7.18 Time‐domain reflectometry comparison.
Figure 7.19 Comparison of eye diagrams at 28 Gbps.
Figure 7.20 Chip‐last HD‐FO packaging vs. FC‐PoP thermal simulation data – st...
Figure 7.21 Chip‐last HD‐FO package vs. FC‐PoP thermal simulation – transient...
Figure 7.22 15 mm body package for reliability data collection.
Figure 7.23 Drop test Weibull results.
Figure 7.24 IC package integration roadmap.
Chapter 8
Figure 8.1 Schematic view of the embedded silicon fan‐out (eSiFO) structure....
Figure 8.2 Process flow of eSiFO package manufacturing.
Figure 8.3 Cross‐sectional view of the cavity after process optimization: (a)...
Figure 8.4 Eight inch reconstructed wafers with different die sizes: (a) 2 mm...
Figure 8.5 The polymer filling of the trench with different widths: (a) 15 μm...
Figure 8.6 Two‐layer RDL for multi‐die integration.
Figure 8.7 eSiFO after BGA formation.
Figure 8.8 An eSiFO package: (a) the outlook and (b) the cross‐sectional micr...
Figure 8.9 3D eSiFO package: (a) frontside and (b) backside.
Figure 8.10 Cross‐sectional view of a 3D eSiFO package.
Figure 8.11 Thermal comparison between eSiFO and eWLB package: (a) thermal re...
Figure 8.12 Electromagnetic simulation of eSiFO package to board transition: ...
Figure 8.13 .Test vehicles for board‐level reliability: (a) the designed eSiF...
Figure 8.14 .Cumulative percentage of daisy chain electric resistances under ...
Chapter 9
Figure 9.1 Overview of embedding technologies.
Figure 9.2 Active and passive components assembled on i
2
Board interposer bef...
Figure 9.3 Different chip assembly methods for chip embedding: on the left is...
Figure 9.4 Face‐up/face‐down assembly.
Figure 9.5 World record for embedded components: six components with 1231 I/O...
Figure 9.6 Interposer with flip‐chip assembly and passive components.
Figure 9.7 Production process of i
2
Board.
Figure 9.8 EMI shielding carried out with ground layers as shields.
Figure 9.9 Daisy chain test principle for IR online testing during TCT.
Figure 9.10 X‐ray image of a 10 mm × 10 mm test vehicle. TCT: Temperature cyc...
Figure 9.11 Prediction graph for resistance change <0.5% after 3000 cycles.
Figure 9.12 Process and test flow for i
2
Board production.
Figure 9.13 Embedded chip in an eight layer multilayer with 0.9 mm total thic...
Figure 9.14 i
2
Fish. A demonstrator for embedding of RFID tags using i
2
Board...
Figure 9.15 Customer samples before (left) and after (right) embedding of an ...
Chapter 10
Figure 10.1 State‐of‐the‐art three‐phase insulated‐gate bipolar transistor (I...
Figure 10.2 Exploded view of a Smart p
2
Pack.
Figure 10.3 Process flow: lead frame with cavities where power devices are as...
Figure 10.4 Lead frame with power MOSFETs assembled into cavities.
Figure 10.5 B6 bridge module. Gate/source connection with copper traces/plane...
Figure 10.6 Cross section of a p
2
Pack with copper‐filled blind vias.
Figure 10.7 Data sheets indicating the
R
dson
(drain to source on state resist...
Figure 10.8 Rdson for TO 263‐7 (right), die on DCB substrate (middle), and p
2
Figure 10.9 Switching characteristic of p
2
Pack (gray) vs. die on DCB (black)...
Figure 10.10 32 kW test vehicle in Smart p
2
Pack technology. IGBT application...
Figure 10.11 Efficiency graph of a 32 kW test vehicle in Smart p
2
Pack techno...
Figure 10.12 Symmetry areas for FE modeling: ¼ of a lead frame assembled with...
Figure 10.13 Temperature distribution and thermal resistance (
R
th
) in a p
2
Pa...
Chapter 11
Figure 11.1 Fan‐out package using a metal base plate.
Figure 11.2 EDS package design characteristics.
Figure 11.3 EDS with pads on both sides of the cross‐sectional structure.
Figure 11.4 Basic FO‐PLP processing steps.
Figure 11.5 EDS processing steps.
Figure 11.6 Area effect of wafer‐level packages on one panel‐level structure....
Figure 11.7 Design rules for a typical EDS package.
Figure 11.8 Example of a standard deep via between topside and bottomside of ...
Figure 11.9 Stacked die EDS structure.
Figure 11.10 Possible EDS alternatives.
Figure 11.11 Thermal performance comparison between an EDS and an FBGA packag...
Figure 11.12 Insertion loss simulation for various packages.
Figure 11.13 Package cross section (a) and reliability test results (b) of FO...
Figure 11.14 Warpage measurements for FO‐PLP design.
Figure 11.15 EDS reliability test matrix.
Figure 11.16 A module using EDS technology.
Figure 11.17 Design rules for an EDS module.
Figure 11.18 Cross‐sectional analysis of an EDS module.
Figure 11.19 Module reliability test matrix and results.
Figure 11.20 Example of an EDS module with WLCSP.
Figure 11.21 Outline of a basic EDS package for power devices: (a) bottom and...
Figure 11.22 Cross‐sectional view of a facedown EDS power package.
Figure 11.23 Fabrication process flow.
Figure 11.24 Package models compared in the electrical characteristics analys...
Figure 11.25 Results of Rds comparison.
Figure 11.26 Results of Lds comparison.
Figure 11.27 Three‐in‐one power module packages. (a) PQFN type and (b) embedd...
Figure 11.28 The results of the thermal simulation. (a) Thermal resistance an...
Figure 11.29 The temperature distribution of the two packages: (a) PQFN as re...
Figure 11.30 Size miniaturization and thermal resistance reduction on power m...
Chapter 12
Figure 12.1 DrBlade1 with small package size and low profile of 5 × 5 × 0.5 m...
Figure 12.2 Schematic cross section of DrBlade1; the color codes indicate the...
Figure 12.3 SEM image of a mechanical cross section through a DrBlade1 packag...
Figure 12.4 μ‐CT image of DrBlade1, topside view.
Figure 12.5 Schematic cross section of the DrBlade2 package.
Figure 12.6 Process flow overview.
Figure 12.7 Top and bottom views of DrBlade2 (left) and DrBlade1 (right).
Figure 12.8 Cross section through simulated voltage (normalized values) withi...
Figure 12.9 Thermal resistance to ambient; Ploss = 4.5 W, TA = 70 °C, eight‐l...
Figure 12.10 Mechanical cross section through a DrBlade2 package at outer row...
Figure 12.11 Cross section through electromigration test vehicle after more t...
Chapter 13
Figure 13.1 Procedure of a chip‐first FO‐WLP process also known as embedded w...
Figure 13.2 Influence of filler loading (content) on LMC properties.
Figure 13.3 Flow mark appearance.
Figure 13.4 Cross‐sectional image of flow mark.
Figure 13.5 The influence of mold thickness and filler size on flow mark appe...
Figure 13.6 Die‐shift phenomenon in molding process.
Figure 13.7 Formulation image for requirement.
Chapter 14
Figure 14.1 Conversion of polyamic acid to polyimide.
Figure 14.2 Positive‐acting PI and PBO.
Figure 14.3 Defects in fine patterning. (a) Positive acting PBO. (b) Negative...
Figure 14.4 Deep gap formability for multilayer structures.
Figure 14.5 Cracking at Cu pad area after TCT.
Figure 14.6 Delamination after immersion in resist stripper.
Figure 14.7 Crack propagation from delamination at the Cu surface.
Figure 14.8 Short circuit after bHAST (20 μm space pattern).
Figure 14.9 Design concept of a low temperature cure material.
Figure 14.10 Correlation between challenges and materials.
Figure 14.11 PBO‐Gen3 resolution on Si and Cu (7 μm thickness after cure). (a...
Figure 14.12 PBO‐Gen3 lithographic performance (cross‐sectional 7 μm thicknes...
Figure 14.13 PBO‐Gen3 thick film formability.
Figure 14.14 Deep gap formability performance.
Figure 14.15 Mechanical properties. Examples of stress–strain curves (25 vs. ...
Figure 14.16 Adhesion stud pull test results on Cu after PCT.
Figure 14.17 Adhesion stud pull test results on PBO/PBO after PCT.
Figure 14.18 Cross sections of (a) PBO‐Gen2 and (b) PBO‐Gen3 on a Cu line aft...
Figure 14.19 PBO‐Gen2 and PBO‐Gen3 appearance (100 μm sq. pattern) after imme...
Figure 14.20 Test vehicle for bHAST.
Figure 14.21 PBO‐Gen3 insulation resistance during bHAST (130 °C/85% RH/3.3 V...
Figure 14.22 Assembly process of FO‐WLP test vehicle used for reliability tes...
Figure 14.23 Cross section of FO‐WLP test vehicle.
Figure 14.24 PI‐Gen1 and PI‐Gen2 topography comparison (after cure).
Figure 14.25 PI‐Gen2 resolution at varying thicknesses after cure.
Figure 14.26 Cross sections of PI‐Gen2 vias (5 and 10 μm resolution).
Figure 14.27 PI‐Gen2 cross sections at varying cure temp. (10 μm space, 10 μm...
Figure 14.28 PI‐Gen2 cross sections on various substrates (10 μm space, 10 μm...
Figure 14.29 PI‐Gen2 mechanical properties. Example of stress–strain curve at...
Figure 14.30 PI‐Gen2 adhesion stud pull test results to Cu after PCT.
Figure 14.31 Adhesion stud pull test results to PI‐Gen2/PI‐Gen2 after PCT.
Figure 14.32 PI‐Gen2 cross sections of Cu line after 100 hours PCT at varying...
Figure 14.33 PI‐Gen2 appearance (100 μm square pattern) after immersion in re...
Figure 14.34 PI‐Gen2 insulation resistance during bHAST (130 °C/85% RH/3.3 V,...
Chapter 15
Figure 15.1 Schematic presentation of building blocks for a photosensitive po...
Figure 15.2 Typical monomers used for the synthesis of polyimide precursors....
Figure 15.3 Schematic presentation of a rigid stiff and flexible polymer back...
Figure 15.4 Correlation table between the cure temperature (high >300 °C, low...
Figure 15.5 Chemical reaction path and corresponding activation energy for im...
Figure 15.6 FTIR analysis indicates that the polyimide precursor is fully imi...
Figure 15.7 Degree of imidization as a function of cure temperature for a rig...
Figure 15.8 Typical process flow for a negative tone low temperature cure pol...
Figure 15.9 Comparison between positive tone and negative tone photosensitive...
Figure 15.10 Microscope image of via openings ranging from 5 up to 30 μm in a...
Figure 15.11 Bossung plot – low temperature cure dielectric.
Figure 15.12 Optical microscope inspection and scanning electron microscopy o...
Figure 15.13 Schematic integration flow of photosensitive polyimide material ...
Figure 15.14 TGA analyses of polyimide film cured at 230 °C (dotted line) and...
Figure 15.15 Chemical resistances of low temperature cure polyimide against s...
Figure 15.16 Stress–strain curve of a 230 °C cured polyimide film.
Figure 15.17 (a) DMA and (b) TMA curves of a 230 °C cured polyimide film.
Figure 15.18 Dielectric constant and dissipation factor over the full frequen...
Figure 15.19 Shear test of PI stud on different substrate types. Study of the...
Figure 15.20 Design guideline at the sawing street to avoid negative dielectr...
Figure 15.21 Schematic presentation for the short loop reliability test matri...
Figure 15.22 Mechanical properties of the LTC 9320 as a function of the PCT t...
Figure 15.23 Solder ball bulk crack at PCB side, which is the top of the pict...
Figure 15.24 Intermetallic crack at the component side for TV A for drop test...
Figure 15.25 Key dielectric trends for advanced packages.
Chapter 16
Figure 16.1 Core capabilities of advanced die attach equipment.
Figure 16.2 90° flipping of a component.
Figure 16.3 Parallel pick handling, implemented in terms of a flipper and a r...
Figure 16.4 Machine sequences for (a) local and (b) global accurate placement...
Figure 16.5 Thermal drift of two handling systems based on repeated position ...
Figure 16.6 Coplanarity setup. (a) – (c) indicate three important alignment a...
Figure 16.7 Pick and place tool manufactured from a single part.
Figure 16.8 Measuring the misalignment of a glass die and glass substrate bas...
Figure 16.9 Integrated standard BMC kit with small glass substrate and refere...
Figure 16.10 Results of a BMC test for a next‐generation dual head fan‐out bo...
Figure 16.11 Large area glass‐on‐carrier process with 5 mm × 5 mm glass die o...
Chapter 17
Figure 17.1 Transfer molding process schemes for single cavity lead‐frame pac...
Figure 17.2 Compression molding scheme of a molded array package (MAP) based ...
Figure 17.3 Comparison of ball on passivation (no RDL) WLP, RDL WLP, and fan‐...
Figure 17.4 From fan‐in to fan‐out technology.
Figure 17.5 The four main processes for creating the reconfigured wafer via c...
Figure 17.6 Flexibility of the eWLB package platform in comparison with the l...
Figure 17.7 Molded wafer encapsulation methods with their pros and cons.
Figure 17.8 eWLB die shift before (left side) and after (right side) optimiza...
Figure 17.9 eWLB warpage before (left side) and after (right side) optimizati...
Figure 17.10 Schematic cross section of a molded wafer with carrier system.
Figure 17.11 Cross‐sectional scheme of the thermal release tape; multiple lay...
Figure 17.12 Adhesion force of a thermal release glue and a pressure‐sensitiv...
Figure 17.13 Carrier system with chips after pick and place (left) and the co...
Figure 17.14 3D sketch of the molded wafer together with the carrier system b...
Figure 17.15 Photo of molded wafer after debonding (left) and the correspondi...
Figure 17.16 Ingredients of molding compounds that are used for encapsulation...
Figure 17.17 Cross section of a typical molding compound for semiconductor de...
Figure 17.18 Molding compound states of aggregation for the compression moldi...
Figure 17.19 Compression molding methods cavity‐down (top) vs. cavity‐up (bot...
Figure 17.20 Viscosity of GMC and LMC material vs. molding process time.
Figure 17.21 Mold flow speed vs. compression speed.
Figure 17.22 Mold tool design for spring‐loaded cavity: during clamping the r...
Figure 17.23 Mold tool design with overflow mechanism: (left) during clamping...
Figure 17.24 Comparison of design rules for transfer molding and compression ...
Figure 17.25 . Carrier system with chips (1), the dispensing of LMC (2), the ...
Figure 17.26 The optimized compression speed (left) in relation to the diamet...
Figure 17.27 The toggle press mechanism was optimized on press clamping force...
Figure 17.28 Cross‐sectional scheme of a transfer mold tool concept including...
Figure 17.29 Compression molding cross‐sectional scheme of a parallel press (...
Figure 17.30 Cross‐sectional scheme of transfer mold tool and how the molding...
Figure 17.31 Cross‐sectional scheme of the molded part thickness: target thic...
Figure 17.32 Transfer molded package with typical irregularities: (left) requ...
Figure 17.33 Sketch of a direct‐drive ball screw press mechanism.
Figure 17.34 Four‐ball screw drive press mechanism that is optimized for prec...
Figure 17.35 Liquid compound dispenser that is optimized for accurate dispens...
Figure 17.36 High performance vacuum pipe system.
Figure 17.37 Top mold tool covered completely with release film.
Figure 17.38 Compression molding equipment optimized for chip embedding (WCM‐...
Figure 17.39 eWLB features with corresponding results for 300 mm molded wafer...
Figure 17.40 Total thickness variation, wafer diameter tolerance, and overall...
Figure 17.41 Front‐end‐like round wafers compared with square back‐end strip ...
Chapter 18
Figure 18.1 Turnkey solution for FO‐WLP.
Figure 18.2 Use of various thin film fan‐out packaging technologies.
Figure 18.3 Illustrations of the major processing steps of various FO‐WLP tec...
Figure 18.4 FO‐WLP die placement tool suitable for various FO‐WLP technologie...
Figure 18.5 Direction of molding.
Figure 18.6 Definition of keep out zone (KoZ).
Figure 18.7 Various dispensing patterns to resolve moldability challenges.
Figure 18.8 Dispensing with
x–y
table movement.
Figure 18.9 Input and output load ports for different substrate formats.
Figure 18.10 Molding press system with convertible mold chase.
Figure 18.11 (a) Dispenser for liquid. (b) Dispenser for granules.
Figure 18.12 SCARA robot handler.
Figure 18.13 All‐in‐one total solution using turret platform with final testi...
Figure 18.14 Contactless précising for aligning package with modules in the
x
...
Figure 18.15
A‐Eye inspection
detecting micro‐crack width with autofoc...
Figure 18.16
iFlip
function reduces the setup time for ultrasmall‐size WLP....
Chapter 19
Figure 19.1 RDL process flow.
Figure 19.2 SPTS 300 mm Sigma
f
×
P
system for FO‐WLP PVD.
Figure 19.3 Example PVD cluster system for FO‐WLP.
Figure 19.4 PVD RDL process flow.
Figure 19.5 RGA mass scan of a 300 mm molded wafer with PI passivation in a v...
Figure 19.6 ICP etch rate deterioration sputter etching pure metal.
Figure 19.7 Particle performance in non‐optimized ICP pre‐clean etching wafer...
Figure 19.8 Contamination of pads during pre‐clean.
Figure 19.9 Bowed 300 mm FO‐WLP molded wafer in equipment front‐end module (E...
Figure 19.10
R
c
performance with increased degas time.
Figure 19.11 Outgassing during pre‐clean: atmospheric vs. vacuum degas pretre...
Figure 19.12 Pre‐clean etch rate stability.
Figure 19.13
In situ
pasting during pre‐clean.
Figure 19.14 VPD metallic contaminant levels using co‐pasting technique.
Figure 19.15 SE‐LTX pre‐clean particle performance with co‐pasting technique ...
Figure 19.16 RC stability using co‐pasting over 350 wafers with no wafer past...
Figure 19.17 ICP vs. diode etch comparison.
Figure 19.18 SPTS Inspira PVD module for UBM and RDL.
Figure 19.19 Backfill cool concept for bowed wafer cooling.
Figure 19.20 Continuous Cu in through‐mold via test structures.
Figure 19.21 FO‐WLP PVD system reliability data.
Figure 19.22 FO‐WLP device test structure
R
c
repeatability.
Chapter 20
Figure 20.1 Schematic illustrations of excimer laser ablation of polymer in a...
Figure 20.2 Top view of dielectric (PBO HD8820) surface post‐ablation (a) and...
Figure 20.3 Example of ablation rates in ABF (GX92), PET, PI (HD4100), and FC...
Figure 20.4 Example beam delivery system schematic for an excimer laser ablat...
Figure 20.5 Schematic description of the dual damascene process for an RDL.
Figure 20.6 SEM image of an embedded RDL and via formed by excimer laser abla...
Figure 20.7 Cross‐sectional view of line and via post‐CMP process and seed la...
Figure 20.8 Process barriers for the POR lithography process flow: (a) topogr...
Figure 20.9 Daisy chain yield over a 200 mm wafer.
Figure 20.10 Excimer laser enabled dual damascene formation in ABF film GY50....
Figure 20.11 Reliability for 8 μm excimer laser ablated micro‐via in ABF GX92...
Figure 20.12 (a) Current POR photolithography process integration flow for on...
Figure 20.13 Process cost comparison results for current POR and dual damasce...
Figure 20.14 Cycle time comparison results for current POR and dual damascene...
Chapter 21
Figure 21.1 Schematic manufacturing process for chip‐first and chip‐last inte...
Figure 21.2 Classification of temporary bonding and debonding processes.
Figure 21.3 (a) Effects of a laser shot sequence with small Gaussian compared...
Figure 21.4 (a) Bright‐field microscope images of UV debonding without overex...
Figure 21.5 Schematic of the temperature evolution during UV DPSS laser debon...
Chapter 22
Figure 22.1 The reconstitution process flow.
Figure 22.2 The eWLCSP structure.
Figure 22.3 The eWLCSP process flow.
Figure 22.4 Micrographs of eWLCSP with sidewall protection.
Figure 22.5 Micrograph of cross section of (a) eWLCSP with 5‐side protection ...
Figure 22.6 TCoB Weibull plot for eWLCSP.
Figure 22.7 Drop test Weibull plot for eWLCSP.
Figure 22.8 Pre‐aligner station where the wafer notch is detected and wafer I...
Figure 22.9 Indexing of eWLCSP carrier in a wafer test of FlexLine.
Figure 22.10 eWLCSP product with protective sidewall coating.
Chapter 23
Figure 23.1 Key metrics used to establish MCP interconnect capabilities. Figu...
Figure 23.2 Technology envelopes for 2D and 2.5D MCP technologies (note that ...
Figure 23.3 Schematic showing the EMIB concept.
Figure 23.4 Top view of a test package highlighting three different designs o...
Figure 23.5 Cross‐sectional image showing the bridge metal layers and interla...
Figure 23.6 Schematic showing key steps in constructing the EMIB package and ...
Figure 23.7 Cross section of a test vehicle showing fine‐pitch and coarse‐pit...
Figure 23.8 Insertion loss of hundreds of samples of a representative EMIB in...
Figure 23.9 Simple I/O driver and unterminated receiver for EMIB interconnect...
Figure 23.10 Eye diagrams of 2 Gbps signaling at channel lengths from 3.2 to ...
Chapter 24
Figure 24.1 Envisioned systems featuring (a) polymer‐enhanced TSVs [28] and (...
Figure 24.2 Polymer‐clad TSVs with a thick SU‐8 liner [30].
Figure 24.3 At 150° C, (a) first principal strain of silicon at the top of TS...
Figure 24.4 Polymer‐embedded vias with copper vias in SU‐8 wells within silic...
Figure 24.5 De‐embedded polymer‐embedded via (PEV) loss using measurements an...
Figure 24.6 (a) Polymer‐embedded coaxial TSVs with ground shield vias and (b)...
Figure 24.7 (a) Fabricated polymer‐enhanced coaxial vias and non‐coaxial vias...
Figure 24.8 (a) Fabricated CMIs and (b) two assembled anchor chips over a sub...
Figure 24.9 Four‐point resistance measurement results of the solder bumps and...
Guide
Cover
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Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies
Edited by
Beth Keser, Ph.D.
and
Steffen Kroehnert
