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Cover
Introduction to the Intelligent Internet of Things
1 Smart Cities as the Prototype of the Intelligent Internet of Things
1. 1.1 Overview
2. 1.2 Smart Cities
3. 1.3 Smart Commerce as an Element of the Smart City
4. 1.4 Smart Residences
5. 1.5 People as Center of Smart Connected Homes
6. 1.6 Smart Individual Transportation
7. 1.7 Smart Transportation Networks
8. 1.8 Smart Energy Networks
9. 1.9 Smart Connected Buildings
10. 1.10 Thoughts
11. References
2 Memory Applications for the Intelligent Internet of Things
1. 2.1 Introduction
2. 2.2 Comparisons of the Various Nonvolatile Embedded Memories Characteristics
3. 2.3 Circuits Using Ultralow Power MCU with Embedded Memory for Energy Harvesting
4. 2.4 Ultralow Power Battery Operated Flash MCU
5. 2.5 Nonvolatile MCUs Using Emerging Memory for Nonvolatile Logic
6. 2.6 Communication Protocols for Memory Sensor Tags
7. 2.7 Wearable Medical Devices
8. 2.8 Low Power Battery Operated Medical Devices and Systems
9. 2.9 Automotive Network Applications
10. 2.10 Smart Electrical Grid and Digital Utility Smart Meters
11. 2.11 Consumer Home Systems and Networks
12. 2.12 Motor Control Chips with Embedded Memory
13. 2.13 Smart Chip Cards in Advanced Applications
14. 2.14 Analysis of Big Data Server Memory Hierarchy for Storing IoT
15. References
3 Embedded Flash and EEPROM for Smart IoT
1. 3.1 Introduction to eFlash and eEEPROM for Smart IoT
2. 3.2 Single Poly Floating Gate eFlash/EEPROM Cells for IoT
3. 3.3 eFlash Cells Using Multiple Single Polysilicon CMOS Logic Transistors
4. 3.4 Split Gate Technology for Floating Gate Embedded Flash
5. 3.5 Stacked Flash and Processor TSV Integration
6. 3.6 OTP/MTP Embedded Flash Cells and Fuses
7. 3.7 Stacked Gate Double Poly Flash
8. 3.8 Charge Trapping eFlash
9. 3.9 Split Gate CT eFlash Nanocrystal Storage
10. 3.10 Novel Embedded Flash Memory
11. References
4 Thin Film Polymer and Flexible Memories
1. 4.1 Overview
2. 4.2 Organic Ferroelectric Memories
3. 4.3 Polymer Ferroelectric Tunnel Junctions
4. 4.4 Types and Characteristics of Polymer Resistive RAMs with Flexible Substrate
5. 4.5 Charge Trapping Nanoparticle (NP) Memory on Flexible Substrates
6. 4.6 Transfer of Conventional Memory Chips on to Flexible Substrates
7. References
5 Neuromorphic Computing Using Emerging NV Memory Devices
1. 5.1 Overview of Resistive RAMs and Ferroelectric RAMs in Neuromorphic Systems
2. 5.2 Various Resistive RAMs for use as Synapses in Neuromorphic Systems
3. 5.3 3D Neuromorphic Memories
4. 5.4 Modeling and Characterization of RRAMs as Synaptic Devices
5. 5.5 Spiking Neural Nets, STDP, Potentiation, and Depression
6. 5.6 Neural Network Systems Using Ferroelectric RAM Technology
7. 5.7 Early Neuromorphic Computers Using Phase Change Memory
8. 5.8 Resistive RAMs in Neuromorphic System Design and Application
9. 5.9 Neuromorphic Memories Using Polymer and Flexible Memories
10. References
6 Big Data Search Engines and Deep Computers
1. 6.1 Overview of Big Data Search Engines and Deep Computers
2. 6.2 Content Addressable Memories Made Using Various Emerging Nonvolatile Memories
3. 6.3 Components of Large Search Engines and Artificial Neural Networks
4. 6.4 Memory Issues in Deep Learning Systems
5. 6.5 Deep Neural Nets for IoT
6. References
7 Memory in Security Issues for IoT
1. 7.1 Introduction to Memory in Security Issues for IoT
2. 7.2 Memories Used as Physical Unclonable Functions (PUFs)
3. 7.3 On‐Chip Memory‐Based Security Systems
4. References
Index
End User License Agreement

List of Tables

Chapter 03
1. Table 3.1 Applications for microcontrollers with embedded nonvolatile memories.
2. Table 3.2 Early single polysilicon floating gate EEPROM features.
3. Table 3.3 Electrical characteristics of the new single poly cell and of eFlash.
4. Table 3.4 Typical operating voltages for a 65 nm split gate Flash cell.
5. Table 3.5 Various application specifications for split gate Flash chips. Based on Lee et al. [41].
6. Table 3.6 Biases for erase, program, and read.
7. Table 3.7 Operating conditions for the 40 nm ESG3 cell.

List of Illustrations

Chapter 01
1. Figure 1.1 Elements of the smart city include connected networks of transportation, commerce, public services, connected residences, and public utilities.
2. Figure 1.2 RFID tag on retail merchandise showing antenna and chip.
3. Figure 1.3 Drone carrying camera with control unit.
4. Figure 1.4 Concept of an intelligent connected home.
5. Figure 1.5 Example of transmitted autofill of grocery list using sensors for a low milk level, NFC for transmission of milk to a grocery list, WiFi for transmission of purchase request to grocery store, followed by delivery of milk to the home.
6. Figure 1.6 Illustration of a possible future wearable system – a wearable blood glucose detector network with an intelligent monitor and connected insulin pump.
7. Figure 1.7 Automotive IoT networks of processors including: body processors, infotainment processors, driving aids, and engine processors.
8. Figure 1.8 Automotive safety assistance devices currently available.
9. Figure 1.9 Photograph of a Texas EZ tag RFID sticker affixed to a windshield.
10. Figure 1.10 Illustration of a smart energy network controlled by smart electrical meters.
11. Figure 1.11 Picture of a “NEST” thermostat for smart buildings and houses.
12. Figure 1.12 Illustration of digital connected systems in a smart hospital environment.
Chapter 02
1. Figure 2.1 Estimate of shipments of MCU chips with embedded nonvolatile memory (BU annually).
2. Figure 2.2 Array capacity versus endurance for various types of embedded Flash memory cells.
3. Figure 2.3 Write endurance (cycles) versus write time (ns) for different memory cell types including: SST‐MRAM, FeRAM, PCM, RRAM, and embedded Flash memory.
4. Figure 2.4 Typical reliability requirements for NV memory embedded in MCU.
5. Figure 2.5 Special reliability requirements for nonvolatile embedded memory in MCU for smart card and automotive applications.
6. Figure 2.6 Automotive system and performance requirements in 2015.
7. Figure 2.7 Smart card and medical sensor requirements.
8. Figure 2.8 Characteristics of an embedded FeRAM MCU for energy harvesting sensor applications.
9. Figure 2.9 Circuit schematic of PVDF piezoelectric vibration energy scavenger cantilever in circuit with FeFET memory.
10. Figure 2.10 Schematic illustration of an FeFET with stacked ZnO/PZT/SrRuO₂ structure.
11. Figure 2.11 Schematic circuit diagram of the 1T1C resistive RAM (RRAM) cell array structure.
12. Figure 2.12 Ultra‐low power IoT battery operated applications used with emerging memory technologies.
13. Figure 2.13 Power lowering techniques for ultralow power battery operated Flash MCU systems.
14. Figure 2.14 Electrical and reliability characteristics of 8‐bit MCU with embedded RRAM for use in battery powered circuits. An oxide RAM (OxRAM) technology was used for the RRAM.
15. Figure 2.15 Power management block diagram of the low power FeRAM MCU.
16. Figure 2.16 Features and target applications of 16‐bit MCU with embedded FeRAM intended for use in battery powered circuits.
17. Figure 2.17 Block diagram of the MCU with eFeRAM.
18. Figure 2.18 Illustration of ferroelectric (FE) capacitors connected to a nonvolatile data flip‐flop (nvDFF).
19. Figure 2.19 System architecture of the MCU showing 32b core and nonvolatile logic (NVL) controller.
20. Figure 2.20 Functional diagram of NVL 32‐bit SoC with FeRAM program and data memory.
21. Figure 2.21 Basic NV latch circuit diagram using magnetic tunnel junction (MTJ) nonvolatile memory elements in CMOS technology.
22. Figure 2.22 Block diagram of nonvolatile 65 KB RAM/ROM unified (2T+1MTJ) SpinRAM MCU.
23. Figure 2.23 VDD versus time of computations in energy harvesting type system with NVDFF showing computations interspersed with times of retained data.
24. Figure 2.24 Conventional master–slave nonvolatile flip‐flop.
25. Figure 2.25 Schematic of (a) OxRAM RRAM stack and (b) CBRAM with HfO₂/GeS₂ electrolyte.
26. Figure 2.26 3D circuit schematic illustration of 7T1R nvSRAM.
27. Figure 2.27 System architecture of the RRAM enabled NV‐processor.
28. Figure 2.28 Schematic diagram of nonvolatile scan flip‐flop.
29. Figure 2.29 Picture of US Passport with the cover closed, with the position of the NFC chip indicated.
30. Figure 2.30 Illustration of retail beacon interacting with individual shopper’s smartphone.
31. Figure 2.31 Characteristics of a typical Bluetooth LE type3 tag.
32. Figure 2.32 Illustration of wireless Bluetooth speaker.
33. Figure 2.33 Office Wi‐Fi router used in the offices at Memory Strategies International.
34. Figure 2.34 Wireless network of medical devices to medical suppliers and monitors.
35. Figure 2.35 Illustration of die layout showing two 64Kb CBRAM macros integrated with the Body Sensor Node (BSN) digital platform.
36. Figure 2.36 Schematic block diagram of a biosignal processor LSI.
37. Figure 2.37 Wearable healthcare system including ECG processor, accelerometer IC, antenna for NFC, and an NFC tag IC.
38. Figure 2.38 Sketch of the ECG processor chip showing 64KB FeRAM.
39. Figure 2.39 Block diagram of an ECG processor with 64KB FeRAM.
40. Figure 2.40 Features of various portable health monitor Flash MCU including nonvolatile memory and electrical characteristics.
41. Figure 2.41 Illustration of commercial wearable blood glucose meter.
42. Figure 2.42 Bluetooth wireless fitness tracker for taking heart rate readings, tracking sleep automatically, and tracking steps.
43. Figure 2.43 Features of Flash MCU with embedded RRAM for low power battery operated portable medical devices.
44. Figure 2.44 Examples of automotive applications, typical MCU, typical embedded NVM capacity for applications, and types of embedded nonvolatile memories used in these applications.
45. Figure 2.45 Illustration of typical ADAS system concepts in an automobile radar system.
46. Figure 2.46 Possible future control system for ADAS and autonomous vehicles.
47. Figure 2.47 Examples of early advanced driver assistance systems.
48. Figure 2.48 Features of memory macro for automotive powertrain applications.
49. Figure 2.49 Operating frequency for an automotive MCU by year showing MONOS and FG Flash.
50. Figure 2.50 Code and data Flash characteristics in 28 nm SG‐MONOS embedded Flash memory.
51. Figure 2.51 Smart meter chips from various vendors showing MCU and embedded nonvolatile memory along with chip active and standby current.
52. Figure 2.52 Illustration of electric meters connected between a home solar generating facility and an electric utility. The meter on the left measures electricity generated by the solar array and the one on the right shows net usage of the community and solar facilities.
53. Figure 2.53 Home network of connected systems with central home automation.
54. Figure 2.54 Memories for tomorrow’s Cloud applications (collected from devices shown at the 2016 ISSCC).
55. Figure 2.55 Memory hierarchy including the storage class memory.
Chapter 03
1. Figure 3.1 Single‐poly EEPROM cell with a thin oxide coupling capacitor and with thin injector oxide: (a) schematic cross‐section and (b) schematic circuit diagram.
2. Figure 3.2 Schematic cross‐sections of single poly CMOS EEPROM cell with NMOS and PMOS transistors with electrically isolated common poly gate showing Fowler‐Nordheim (FN) program and erase: (a) program, (b) erase, and (c) read.
3. Figure 3.3 Circuit diagram of two single poly embedded Flash cells: (a) IBM and (b) Bell Labs.
4. Figure 3.4 Top view of layout of (a) IBM 2T single poly EEPROM and (b) Lucent 3T single poly EEPROM with M3 erase gate added.
5. Figure 3.5 Cross‐section view of 3T single poly embedded Flash cell.
6. Figure 3.6 High voltage NMOS device fully compatible with standard CMOS process.
7. Figure 3.7 Threshold window of single poly EEPROM made in SOI Technology. , November 1997 [8].
8. Figure 3.8 Illustration of silicon nitride side spacer EEPROM operation for (a) program by channel hot electron injection (CHEI), (b) erase by avalanche hot hole injection (AHHI), and (c) read.
9. Figure 3.9 Single poly 4T cell in conventional CMOS showing (a) schematic drawing of the cell structure and (b) schematic circuit diagram of the embedded Flash memory cell.
10. Figure 3.10 Logic eNVM MTP cell: (a) schematic cross‐section and (b) schematic circuit diagram of a unit bit‐cell.
11. Figure 3.11 Logic eNVM cell data retention degradation trend of bit cell current in the erase state after 10,000 program/erase (P/E) cycles.
12. Figure 3.12 “Half‐MOS” device: (a) layout, (b) cross‐section and (c) cell schematic circuit diagram.
13. Figure 3.13 “Half‐MOS” bit cell schematic cross‐section.
14. Figure 3.14 Twin transistor memory cell using HiK logic NMOS process.
15. Figure 3.15 Schematic cross‐section of (a) P‐finger coupling cell and (b) W‐finger coupling cell.
16. Figure 3.16 Single polysilicon EEPROM cell made in conventional CMOS with pMOS tunneling device used for programming and erase, and nMOS transistor used for read and select.
17. Figure 3.17 Schematic cross‐section of pMOS tunneling device.
18. Figure 3.18 Schematic circuit diagram of select gate lateral coupling (SGLC) eNVM cell where C _ch is the floating gate (FG) to substrate capacitance and C _sg is the FG to select gate (SG) lateral capacitance.
19. Figure 3.19 Schematic circuit diagram of 5T logic compatible single poly embedded Flash cell.
20. Figure 3.20 5T configuration macro: (a) erase bias and (b) program bias with neighboring cell having program inhibited via self‐boosting.
21. Figure 3.21 Schematic circuit diagram of 65 nm single poly (a) 3T eFlash cell compared to (b) 5T eFlash which eliminates erase disturb.
22. Figure 3.22 Erase of P‐channel 3T single poly eFlash cell with Fowler‐Nordheim electron tunneling into the floating gate of M2.
23. Figure 3.23 Programming of P‐channel 3T single poly eFlash cell with electron Fowler‐Nordheim tunneling from the floating gate of M3.
24. Figure 3.24 5T schematic circuit diagrams of the P‐channel single poly P‐channel macros with applied (a) erase bias and (b) program bias with program inhibited via self‐boosting.
25. Figure 3.25 Schematic circuit diagrams of (a) original 5T eFlash and (b) 6T eFlash with improved endurance.
26. Figure 3.26 Cross‐Section of split gate Flash EEPROM cell.
27. Figure 3.27 Cross‐section showing (a) erase and (b) program of split gate cell.
28. Figure 3.28 Schematic cross‐section of the 65 nm split gate Flash cell with SSI program and poly‐to‐poly Fowler‐Nordheim erase.
29. Figure 3.29 Schematic cross‐section of split gate Flash cell in 65 nm high performance CMOS logic.
30. Figure 3.30 SST split gate “Super” Flash. Illustrations of (a) first generation, (b) second generation and (c) third generation technology cells.
31. Figure 3.31 Schematic cross‐section of 45 nm logic compatible triple poly split gate cell.
32. Figure 3.32 Split gate Flash SCE and programmable array switch.
33. Figure 3.33 Schematic cross‐section of a third generation split gate memory cell showing oxides associated with programming and erase.
34. Figure 3.34 Schematic cross‐section of vertical 2‐bit/cell split gate embedded Flash memory with shared bit‐lines.
35. Figure 3.35 Common source Flash array with split gate Flash cell.
36. Figure 3.36 Illustration of schematic cross‐section of 55 nm split gate eFlash cell used for compact SPICE model.
37. Figure 3.37 Logic compatible split gate Flash cell in 55 nm logic process.
38. Figure 3.38 Twin bit cell: (a) schematic circuit diagram and (b) schematic cross‐section.
39. Figure 3.39 Block diagram of architecture of the embedded EEPROM.
40. Figure 3.40 Cross‐section of (a) basic split gate SG‐MONOS cell and (b) SG‐HS3P floating gate cell.
41. Figure 3.41 Schematic cross‐section of ESF3 cell in bit‐line direction.
42. Figure 3.42 Schematic of SG cell and schematic showing resistive effect of off‐set spacer.
43. Figure 3.43 ESG3 cell with program disturb mechanisms shown.
44. Figure 3.44 Illustration of stacked chip integration with an interposer with TSV.
45. Figure 3.45 Schematic circuit diagram of the MTP memory.
46. Figure 3.46 Schematic cross‐sections of (a) 28 nm SiO₂ poly‐silicon nMOSFET gate and (b) HfO₂ HKMG nMOSFET gate.
47. Figure 3.47 Characteristics of gate current for gate dielectric anti‐fuse and HKMG dielectric fuse.
48. Figure 3.48 Schematic cross‐section showing read operation of (a) conventional eFlash cell with location of high field stress on the tunnel oxide indicated by the dot and (b) reversed eFlash cell with reduced stress on the tunnel oxide.
49. Figure 3.49 Schematic cross‐section of DDC transistor showing undoped epitaxial layer and V_t setting layer
50. Figure 3.50 Schematic process flow for an embedded NVM in base‐line CMOS. Bullets in dashed boxes are part of the conventional CMOS process. Bullets in double outlined boxes are added depositions and italicized bullets are added etches.
51. Figure 3.51 A block diagram of the 130 nm platform in bipolar, CMOS, and DMOS (BCD) is shown.
52. Figure 3.52 Top‐down schematic view of layout of eNOR Flash cell.
53. Figure 3.53 Schematic cross‐section of twin MONOS cells.
54. Figure 3.54 Split gate local SONOS cell in conventional CMOS logic: (a) top‐down view showing localized ONO layer and (b) schematic cross‐section showing Halo implant junction engineering on the source side.
55. Figure 3.55 Illustration of location of BTBT generation and electron acceleration in SONOS cell.
56. Figure 3.56 SG‐MONOS eFlash cell: (a) cell architecture and (b) operational voltage.
57. Figure 3.57 Schematic cross‐section of the SG‐MONOS cell with operating condition voltages for (a) program, (b) erase, and (c) read.
58. Figure 3.58 Split gate MONOS cell showing high voltage only on memory gate for P/E.
59. Figure 3.59 Cross‐section of MG‐SONOS cell showing (a) SSI program and (b) BTBT erase.
60. Figure 3.60 Schematic cross‐section of 90 nm 1T MONOS eFlash Cell.
61. Figure 3.61 Block diagram of low power Flash MCU with 1T‐MONOS aacro.
62. Figure 3.62 Schematic process flow of formation of the fin of the FinFET and the SG‐MONOS.
63. Figure 3.63 Schematic of integration of FinFET SG‐MONOS and logic FinFET CMOS.
64. Figure 3.64 Schematic of embedded charge‐trapping “Mirror‐Bit” Flash cell.
65. Figure 3.65 Schematic cross‐section of the 55 nm SONOS eNVM cell showing the ONO layer and the Salicide.
66. Figure 3.66 Program/erase pulse width of SONOS eNVM technology.
67. Figure 3.67 Schematic circuit diagram of the self‐aligned nitride (SAN) logic non‐volatile memory cell.
68. Figure 3.68 Decrease in charge pumping current after recovery due to reduction of interface traps.
69. Figure 3.69 Read current ratio after 300 P/E cycles with and without periodic DC recovery.
70. Figure 3.70 Schematic cross‐section of asymmetrical tunnel window (ATW) floating gate memory cell.
71. Figure 3.71 Schematic cross‐section of the DT BE‐SONOS stack.
72. Figure 3.72 Schematic of Schottky barrier charge trapping cell with two‐bit operation shown.
73. Figure 3.73 P‐MOS memory transistor with SiGe buried channel with different Ge content
74. Figure 3.74 I–V curve for ZnO charge trap Flash using resistive switching.
75. Figure 3.75 Schematic cross‐section of charge trapping IGZO NVM transistor.
76. Figure 3.76 Schematic cross‐section of FinFET MANOS Flash device fabrication process flow.
77. Figure 3.77 Band diagram of (a) trapping of carriers into the oxygen vacancy traps and (b) detrapping of carriers out of the oxygen vacancy traps.
78. Figure 3.78 Schematic circuit diagram illustrating twin‐cell method.
79. Figure 3.79 Split gate embedded Flash memory where nitride storage is replaced with nanocrystal storage.
80. Figure 3.80 Nonvolatile memory with nanoparticles in V‐groove: (a) cross‐section and (b) top‐down view.
81. Figure 3.81 I_d–V_g characteristics with V_d = 0.2 V for V‐groove channel with and without NPs.
82. Figure 3.82 Schematic circuit diagram of the 1T1B one‐time‐programmable (OTP) array.
83. Figure 3.83 Top and cross‐sectional view of nanogap memory.
Chapter 04
1. Figure 4.1 Illustration of different fields in P(VDF‐TrFE) FeRAMs: (a) applied write field, (b) the resulting imprinted field, and (c) the switching write field.
2. Figure 4.2 Illustrations of domains of copolymer and terpolymer. The terpolymer was obtained by inserting a small amount of chlorofluoroethylene (CFE) in the copolymer.
3. Figure 4.3 Schematic cross‐section of a flexible a‐InGaZnO memory TFT with a P(VDF‐TrFE) gate insulator layer.
4. Figure 4.4 Cross‐sectional view of low temperature process for 2T2C FeRAM array.
5. Figure 4.5 A schematic cross‐section of the screen‐printed complementary gate.
6. Figure 4.6 6T SRAM of organic transistors.
7. Figure 4.7 Block diagram of print programmable ROM.
8. Figure 4.8 Illustration of a bottle of wine with a barcode, QR Code, and ID number, which permits the consumer to use a smartphone to ensure the authenticity of the wine and gain information about it. Photo by B. Prince.
9. Figure 4.9 Characteristics of the various TFT technologies including: amorphous silicon, metal oxide RRAM, self‐assembly monolayer (SAM) organic and inkjet organic.
10. Figure 4.10 Schematic circuit diagram of liquid crystal display pixel architecture using two TFTs, two ferroelectric TFTs, and two capacitors.
11. Figure 4.11 Schematic cross‐section of Al/parylene‐C/parylene‐C/W cell.
12. Figure 4.12 Illustration of I–V curve of typical Al/parylene‐C/W RRAM device.
13. Figure 4.13 Copper atom switch stack with PSE and Al_1‐_x Ti_xO_y layers sandwiched between Ru and Cu electrodes.
14. Figure 4.14 Atom switch physical operating mechanism.
15. Figure 4.15 Signal current for two terminal Cu atom switches (CASs) in (a) ON state and (b) OFF state.
16. Figure 4.16 Programming the two terminal Cu atom switches (CASs): (a) left side and (b) right side. Based on N.
17. Figure 4.17 Illustration of polymer solid electrolyte BEOL Cu atom switch (CAS), which is between M4 and M5.
18. Figure 4.18 Illustration of swept I–V curve of Ni/GeOs/TiO_y/TaN flexible RRAM device on flexible polyimide. A read is shown at 0.5 V with low resistance state (LRS) and high resistance state (HRS) shown.
19. Figure 4.19 Illustration of I–V curve of Pt/HfO_x/parylene‐C/Al structure.
20. Figure 4.20 A resistive switching filamentary model of an Al₂O₃/ArO₃ flexible device: (a) set and (b) reset.
21. Figure 4.21 Four mask a‐IGZO TFTs with top gate top contact on flexible polyimide substrate in (a) coplanar configuration and (b) staggered configuration.
22. Figure 4.22 I–V curve of a‐IGZO RRAM memory showing three resistance states.
23. Figure 4.23 Illustration of the bipolar I–V curve of a flexible Au/BiFeO₃/Pt/Ti RRAM.
24. Figure 4.24 Equivalent circuit of an organic ITO/Alq3/Ag Memory Device where Alq3 is chemically C₂₇H₁₈AlN₃O₃ and ITO is indium–tin oxide.
25. Figure 4.25 Schematic showing the switching process showing: (a) forming, (b) ON/OFF, (c) OFF/ON.
26. Figure 4.26 Three terminal resistive change devices in TFT configuration with AZO channel.
27. Figure 4.27 Bipolar resistive switching I–V characteristics of Al/Al₂O₃/AZO/ITO structure between top electrode (TE) and the source (S) and drain (D).
28. Figure 4.28 Illustration of 1 mm² HfO₂‐based RRAM with 50 nm thick Au BED, 200 nm thick HfO₂ dielectric, and 700 nm thick Ag top electrode.
29. Figure 4.29 Stack of flexible RRAM devices based on simple spin‐coated Sol Gel derived strontium titanate nickelate thin film on polymer substrate.
30. Figure 4.30 Illustration of the resistive switching mechanism model of the STN‐based RRAM in the (a) pristine, (b) LRS, and (c) HRS conditions.
31. Figure 4.31 Schematic of a polymer carbon nanotube charge trapping memory using a thin parylene layer separating the SiO₂/nanotube interface from a photosentive polymer coating.
32. Figure 4.32 I–V switching characteristics on a semilog scale showing hysteresis curve of MIMb consisting of Ag NWPMSSQ/GQD/PMSSQITOPET.
33. Figure 4.33 Band diagrams for (a) the write and (b) erase processes.
34. Figure 4.34 Typical DC current–voltage hysteresis loop for a TiN/Ti/TiO₂_‐x/Au RRAM device (a) with 3 nm Pt NP (solid line) and (b) without NP (dotted line).
35. Figure 4.35 Transparent memory stack with polymer/ZnO nanoparticles for storage.
36. Figure 4.36 Illustrations of I–V curves of (a) TaN/Al₂O₃:Ag:ZnO/ITO RRAM devices with Ag nanoparticles (NP) and of I–V curves of (b) TaN/Al₂O₃/ZnO/ITO RRAM devices without Ag NP.
37. Figure 4.37 Schematic cross‐section of a floating gate memory with an MoS2 channel with an Au nanoparticle charge trapping layer.
38. Figure 4.38 Schematic representation of the wafer thinning and transfer process.
39. Figure 4.39 I–V curves of programmed and erased states of a cell in the flexible NAND Flash.
40. Figure 4.40 Redistribution of interconnects over base of extended fan‐out WL package: (a) single layer of redistribution and (b) two layers of redistribution.
41. Figure 4.41 Advanced fan‐out–wafer level packaging (FO‐WLP) in (a) fan‐out package‐on‐package (FO‐PoP) and (b) fan‐out single‐in‐line package (FO‐SiP).
42. Figure 4.42 Fan‐out wafer level packaging process: (a) application of tape, (b) chip placement, (c) wafer level molding, (d) release from carrier, (e) redistribution and bumping, and (f) singulation.
43. Figure 4.43 Concept of adaptive probing: (a) traditional fixed probing and (b) adaptive probing with probing depth set according to initial test results.
44. Figure 4.44 Failure mechanism for fan‐out but not for fan‐in wafer level packaging: (a) example of cracking on fan‐out wafer and (b) illustration of no cracking on fan‐in wafer.
45. Figure 4.45 An overmolded FO‐WLP with 490 µm thickness and two thin FO‐WLP both ground to 200 µm thickness. On wafer 3 a thin backside protection tape was laminated.
46. Figure 4.46 Illustration of process flow for temporary bonding before and after the laser ablation process.
Chapter 05
1. Figure 5.1 Resistance versus pulse number for an MO‐RRAM: (a) an abrupt SET and (b) a gradual RESET operation.
2. Figure 5.2 Schematic illustration of plausible mechanism of multilevel states of conductance: (a) initial filament (SET), (b) RESET with partially ruptured conductive filament, and (c) second SET with thicker conductive filament.
3. Figure 5.3 Schematic cross‐sections of (a) a metal oxide MO‐RAM in 28 nm CMOS and (b) a CB‐RAM in 130 nm CMOS.
4. Figure 5.4 I–V curve for electronic synapse CBRAM device using Pt/GeSO/TiN Stack with gradually increasing set pulse voltages and pulse widths resulting in a continuous multilevel effect, Based on W. Zhang (Xidian University, NCKU, National Sun Yet‐sen University, Xiamen University, NCTU), IEEE Electron Device Letters, August 2015 [6].
5. Figure 5.5 Illustration of RRAM I–V curves at different sweep voltages showing potential for analog behavior of a PCMO RRAM.
6. Figure 5.6 Illustration of potentiation and depression curves for PCMO‐RRAM. Potentiation voltage is –3 V and depression voltage is +3 V.
7. Figure 5.7 Schematic circuit of simulated neuromorphic system with applied signal waveforms.
8. Figure 5.8 Energy band diagram of Si/Si₃N₄/HfO₂/Al₂O₃/Al cell.
9. Figure 5.9 Example of 3D transistor level monolithic integration.
10. Figure 5.10 Current output versus time for upper and lower devices illustrating good matching between the two.
11. Figure 5.11 Simulated neuromorphic network showing synapse of “N” VRRAM cells.
12. Figure 5.12 Neural circuit with V‐CBRAM pillars having m levels sharing a common transistor.
13. Figure 5.13 Schematic cross‐section of 3D vertical RRAM integrated with FinFET.
14. Figure 5.14 Monolithic integration of RRAM crossbars with shared middle electrodes.
15. Figure 5.15 A typical testing procedure for RRAM devices that switch between highly distinct resistive states.
16. Figure 5.16 Simulated potential for different types of RRAM devices: (a) filamentary showing electric potential drop with increasing gap and (b) nonfilamentary RRAM device.
17. Figure 5.17 Schematic flowchart for simulation of analog switching in an oxide‐based nonfilamentary RRAM.
18. Figure 5.18 Circuit schematics of (a) a 2T1R synapse and (b) a 1T1R synapse.
19. Figure 5.19 Circuit of 1T1R synapse connecting PRE and POST in a spike‐timing dependent plasticity (STDP) integrate and fire network.
20. Figure 5.20 Waveforms of V _g and V _te for (a) potentiation (Δt > 0) and (b) depression (Δt < 0).
21. Figure 5.21 1T1R synapse: (a) circuit connected to PRE and POST and (b) typical spike signals.
22. Figure 5.22 STDP characteristics: change of conductance versus Δt.
23. Figure 5.23 Circuit diagram using RRAM 1T1R crossbar array, which eliminates sneak paths. A differential pair is used as a synapse as illustrated.
24. Figure 5.24 Schematic of single‐layer bipolar neuron network.
25. Figure 5.25 The final resistance distribution of each column.
26. Figure 5.26 Illustration of potentiation and depression characteristics of Mo/PCMO.
27. Figure 5.27 NbO₂ IMT oscillator neuron threshold shifting I–V characteristics.
28. Figure 5.28 Oscillator characteristics of IMT neuron with varying bias conditions. Oscillations above the 1.3 V critical threshold voltage are shown.
29. Figure 5.29 STDP demonstration with CMOS neurons connected using a single CBRAM synapse.
30. Figure 5.30 Change in CBRAM conductance versus spike timing difference with on‐chip CBRAM.
31. Figure 5.31 Architecture for handwritten digits recognition.
32. Figure 5.32 Comparison of voltage and current pulse modes for current pulse program power showing conductance in siemens.
33. Figure 5.33 Principal circuit used to reproduce STP and LTP rules for an OxRAM cell. The circuit imitates the synapse between neuron (i) and neuron (j). Buffer Y(t) modifies the synapse for either STP or LTP rules.
34. Figure 5.34 Schematic cross‐section of CMOS circuit and 3T FeMEM.
35. Figure 5.35 Synaptic weight change of 3T‐FeMEM versus relative timing of pre/post‐spikes with spike width of V _post at 5 µs.
36. Figure 5.36 Two neuron circuit connected by a synapse containing a 3T‐FeMEM and a selector. The first neuron outputs to the synapse a single rectangle pulse to the 3T‐FeMEM and a triple rectangle pulse to the selector. The single rectangle pulse is fed back to the synapse as post‐pulse 1.
37. Figure 5.37 Typical neuromorphic network for an STDP application using ferroelectric tunnel memories for synapsis.
38. Figure 5.38 Single PCM cell DC switching.
39. Figure 5.39 Illustration of gradual SET characteristics of a single cell.
40. Figure 5.40 Illustration of neuromorphic circuits in (a) LIF mode and (b) STDP mode.
41. Figure 5.41 Illustration of the RESET current versus SET resistance for a PCM.
42. Figure 5.42 Conductance change as a function of voltage pulse width “t”.
43. Figure 5.43 Illustration of neuromorphic system of CMOS neurons and RRAM synapses.
44. Figure 5.44 An illustration of neuromorphic non‐von Neumann computing.
45. Figure 5.45 Schematic diagram of self‐assembled flexible IZO transistors.
46. Figure 5.46 Schematic cross‐section of TaN/Al₂O₃:Ag:AnO/ITO RRAM on flexible substrate.
47. Figure 5.47 RRAM pulse response with Ag nanoparticle: (a) potentiation sweep and (b) depression sweep.
Chapter 06
1. Figure 6.1 TCAM cells: (a) 16‐transistor SRAM cell plus NVM and (b) bidirectional voltage divider control for a 3T1R nonvolatile TCAM using MLC RRAM.
2. Figure 6.2 Circuit diagram of nvTCAM search engine using RRAM for data storage.
3. Figure 6.3 Perpendicular magnetic anisotropy (PMA)‐based five‐layer TCAM MTJ with two pinned layers and one free layer.
4. Figure 6.4 Block diagram of TCAM using PentaMTJ cell, a pre‐charge sense amplifier (PCSA) for sensing the difference between two states of resistance, a reference resistance, and a logic circuit.
5. Figure 6.5 Block schematic of spin CAM architecture of a DRAM cell with embedded MRAM.
6. Figure 6.6 Schematic CAM circuit showing an MRAM refreshing DRAM circuit.
7. Figure 6.7 Circuit schematic of the 1T2R memory unit with 1T and 2RRAMs which act as a complementary resistive switching (CRS) device.
8. Figure 6.8 Schematic cross‐section of 2D filament model of HfO_x‐based RRAM.
9. Figure 6.9 Schematic circuit diagram of crossbar architecture for learning system using STT‐MRAM synapses and leaky integrate and fire (LIF) neurons.
10. Figure 6.10 Schematic of the compound spintronic device showing “n” multilevel states.
11. Figure 6.11 Illustration of a compound spintronic neuron using multiple MTJs to implement a multiple step transfer function.
12. Figure 6.12 Block diagram of SRAM accelerator using CMOS SRAM‐based synaptic arrays.
13. Figure 6.13 RRAM accelerator with pseudo‐crossbar array core.
14. Figure 6.14 Illustration of read and write energy per operation for SRAM and RRAM.
15. Figure 6.15 Illustration of extracted HRS/R_off lognormal distributions for filamentary RRAM devices.
16. Figure 6.16 Illustration of training block in RRAM extreme learning machine (ELM) architecture, where H is the hidden layer neuron output and T is the expected output. Both are stored inside the training block.
17. Figure 6.17 Illustration of I–V characteristics of an oxide‐based RRAM device.
18. Figure 6.18 Illustration of: (a) three‐layer perceptron network, with neurons represented as circles and lines as synaptic weights, and (b) synaptic weights, represented as conductance differences between pairs of nonvolatile memory (NVM) devices.
19. Figure 6.19 Top‐level block diagram of a deep convolutional neural network SoC test chip.
20. Figure 6.20 Illustration of a convolutional neural net (CNN) convolution layer.
21. Figure 6.21 Illustration of convolutional neural ets: (a) CNN fully connected layers (FCL) and (b) recurrent neural nets (RNN).
22. Figure 6.22 Block diagram of deep neural processing unit (DNPU).
23. Figure 6.23 System block diagram of 28 nm SoC with deep neural net (DNN) engine for interpretation of noisy real world data from IoT devices.
24. Figure 6.24 Block diagram of power‐gated automatic speech recognition deep neural net chip.
25. Figure 6.25 Block diagram of feedforward DNN accelerator using an SIMD neural network evaluator.
26. Figure 6.26 Block diagram of top‐level architecture of a CNN processor with efficiencies up to 10 TOPS/W.
27. Figure 6.27 Overall block architecture with face image sensor and CNN processor.
28. Figure 6.28 Top‐level diagram of the deep learning accelerator (DLA).
29. Figure 6.29 SRAM synaptic drowsy mode.
30. Figure 6.30 Block diagram showing architecture of NGS processor.
Chapter 07
1. Figure 7.1 Simulated resistance distribution in LRS and HRS of TaO_x‐based RRAM PUF.
2. Figure 7.2 Circuit diagram of PUF implementation based on RRAM resistance variability.
3. Figure 7.3 Retention time versus 1/KT for a single cell PUF response and retention time for a PUF response bit represented by different numbers of cells along with retention degradation over time for eight cells per bit along with an extrapolated retention time at 85 and 27 °C using E_a = 1.15 eV.
4. Figure 7.4 Circuit with two RRAM cells “P” and “Q” connected in parallel where both cells have a 1T+1R configuration. (a) The circuit diagram of the parallel RESET circuit with the two RRAM cells connected in parallel and the output feeding into a comparator. (b) Timing diagrams showing the sequence of applied signals on P and Q. The cells are first SET using a positive voltage from P and Q to the output. They are then RESET using a negative voltage across P and Q to the output for RESET. P and Q are then READ using the voltage divider configuration. Based on S.
5. Figure 7.5 (a) Cumulative distribution function (CDF) of resistance after SET and after RESET for cells P and Q and (b) corresponding distribution of V_out and V_out2 with and without comparator.
6. Figure 7.6 Illustration of an RRAM crossbar array with each PUF bit represented by two RRAM cells.
7. Figure 7.7 Illustration of the MO‐RRAM SET and RESET operation showing the initial forming of the conductive filament, the RESET operation with dissolution of the filament and the SET operation with reform of the filament in the gap left during RESET.
8. Figure 7.8 RRAM memory I–V curve showing the compliance current level that limits SET current for the low resistance state (LRS) and the bipolarity of applying the opposite voltage for RESET to the high resistance state (HRS).
9. Figure 7.9 Schematic circuit diagram of the proposed PUF based on an RRAM array.
10. Figure 7.10 Magnetic tunnel junction (MTJ): (a) Resistance–voltage characteristics of MTJ. Switching from AP > P when I > I_c (AP > P) and from P > AP when I > I_c:(P > AP). (b) 1T1MTJ cell circuit schematic.
11. Figure 7.11 Schematic view of PUF extraction from collected MTJ voltage data categorized into three alternatives representing the parallel state (white), 50% parallel or anti‐parellel state (gray) and anti‐parallel state (black).
12. Figure 7.12 Concept of MRAM PUF authentication protocol. In this system, X is the hardware device that processes the signals between the PUF and the circuit for authentication.
13. Figure 7.13 Schematic circuit diagram pf complementary polarizer spin dice (CPSD) consisting of a single free layer, a tunneling oxide layer, and two complementary polarized pinned layers.
14. Figure 7.14 Diagrams of V_read versus V_th for the GAA SONOS Flash memories showing: (a) erase and programmed state distributions and (b) erased versus V_puf as the statistical median V_th of the programmed state.
15. Figure 7.15 Schematic cross‐section of the 1T1R CB‐RAM cell formed in the metal layers above the transistor.
16. Figure 7.16 8MB STT MRAM cache with process variations: (a) write latency distribution and (b) read latency distribution. Long read/write latency gives a wide attack window for an adversary.
17. Figure 7.17 Architecture of a state‐of‐the‐art face detection model. It includes: scaling, channel generation, integral channel computation, classifier output computation, and nonmaximum suppression states to suppress redundancies.