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<p>Quotation vii</p> <p>Preface ix</p> <p>Introduction xiii</p> <p><b>Chapter 1. The Function of Computation </b><b>1</b></p> <p>1.1. Beginnings 2</p> <p>1.2. Classes of computers 10</p> <p>1.3. Analog approach 36</p> <p>1.4. Hardware–software relationship 37</p> <p>1.5. Integration and its limits 43</p> <p>1.6. Conclusion 47</p> <p><b>Chapter 2. The Function of Memory </b><b>49</b></p> <p>2.1. Definition 50</p> <p>2.2. Related concepts 56</p> <p>2.2.1. A story of endianness 56</p> <p>2.2.2. Alignment 56</p> <p>2.3. Modeling 57</p> <p>2.4. Classification 59</p> <p>2.5. Conclusion 61</p> <p><b>Chapter 3. Computation Model and Architecture: Illustration with the von Neumann Approach </b><b>63</b></p> <p>3.1. Basic concepts 64</p> <p>3.1.1. The idea of a program 64</p> <p>3.1.2. Control and data flows and mechanisms 65</p> <p>3.1.3. Models of computation 67</p> <p>3.1.4. Architectures 72</p> <p>3.1.5. The semantic gap 80</p> <p>3.2. The original von Neumann machine 81</p> <p>3.2.1. von Neumann’s computation model 81</p> <p>3.2.2. von Neumann’s (machine) architecture 82</p> <p>3.2.3. Control 89</p> <p>3.3. Modern von Neumann machines 90</p> <p>3.3.1. Abstraction level 91</p> <p>3.3.2. Base execution outline 97</p> <p>3.3.3. Possible transfers 100</p> <p>3.3.4. Summary: advantages and disadvantages of this model 102</p> <p>3.4. Variations on a theme 104</p> <p>3.4.1. Classification by bus 104</p> <p>3.4.2. Harvard architectures 111</p> <p>3.4.3. Parallelism 113</p> <p>3.5. Instruction set architecture 117</p> <p>3.5.1. Storage components 118</p> <p>3.5.2. Data format and type 126</p> <p>3.5.3. Instruction set 126</p> <p>3.5.4. Memory model 127</p> <p>3.5.5. Execution modes 128</p> <p>3.5.6. Miscellaneous 128</p> <p>3.6. Basic definitions for this book 128</p> <p>3.7. Conclusion 129</p> <p>Conclusion of Volume 1 131</p> <p>Exercises 133</p> <p>Acronyms 135</p> <p>References 153</p> <p>Index 173</p>

<p><b>Philippe Darche</b> is Maître de conférences in Information Technology at the Institut Universitaire de Technologie (IUT) de Paris and a researcher at LIP6 at Sorbonne University in the Inria DeLyS (DistributEd aLgorithms and sYstemS) team, France. He is the author of five books in the field of computer architecture.</p>

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