ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies. New features in the 2nd edition: Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs. Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS. Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, inter-digitation, and common centroid techniques. Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5. Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges. ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit & semiconductor engineers and quality, reliability &analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.
About the Author xixPreface xxiAcknowledgments xxv1 Electrostatic Discharge 11.1 Electricity and Electrostatic Discharge 11.2 Fundamental Concepts of ESD Design 111.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 181.4 ESD Models 191.5 ESD and System-Level Test Models 281.6 Time Constants 391.7 Capacitance, Resistance, and Inductance and ESD 591.8 Rules of Thumb and ESD 621.9 ESD Scaling 631.10 Lumped versus Distributed Analysis and ESD 651.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 791.12 ESD Quality and Reliability Business Metrics 841.13 Twelve Steps to Building an ESD Strategy 851.14 Summary and Closing Comments 86Problems 87References 872 Design Synthesis 942.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 942.2 Electrical and Spatial Connectivity 952.3 ESD, Latchup, and Noise 962.4 Interface Circuits and ESD Elements 982.5 ESD Power Clamp Networks 1012.6 ESD Rail-to-Rail Networks 1052.7 Guard Rings 1092.8 Pads, Floating Pads, and No-connect Pads 1112.9 Structures under Bond Pads 1122.10 Mixed Signal Architecture: CMOS 1122.11 MS Architecture: Digital, Analog, and RF Architecture 1162.12 Digital-to-Analog Interdomain Signal Line Failures 1182.13 Summary and Closing Comments 124Problems 124References 1253 MOSFET ESD Design 1293.1 Basic ESD Design Concepts 1293.2 ESD MOSFET Design: Channel Length 1363.3 N-Channel MOSFET Design: Channel Width 1433.4 ESD MOSFET Design: Contacts 1443.5 ESD MOSFET Design: Metal Distribution 1533.6 ESD MOSFET Design: Silicide Masking 1653.7 ESD MOSFET Design: Series Cascode Configurations 1703.8 ESD MOSFET Design: Multifinger MOSFET Design—Integration of Coupling and Ballasting Techniques 1743.9 ESD MOSFET Design: Enclosed Drain Design Practice 1813.10 ESD MOSFET Interconnect Ballasting Design 1823.11 ESD MOSFET Design: Source and Drain Segmentation 1843.12 MOSFET Design for Analog Applications 1853.13 Summary and Closing Comments 187Problems 187References 1884 ESD Design: Diode Design 1914.1 ESD Diode Design: ESD Basics 1914.2 ESD Diode Anode Design 1944.3 ESD Diode Design: Interconnect Wiring 2024.4 ESD Design: Polysilicon-Bound Diode Designs 2104.5 N-Well Diode Design 2134.6 N+/P Substrate Diode Design 2164.7 ESD Design: Diode String Design 2174.8 Triple-Well ESD Diode Design 2314.9 Summary and Closing Comments 234Problems 234References 2365 ESD Design: Passive Resistors 2395.1 N-Well Resistors 2395.2 N-Diffusion Resistor Design 2485.3 P-Diffusion Resistor Design 2525.4 BR 2545.5 Summary and Closing Comments 268Problems 268References 2706 Passives for Digital, Analog, and RF Applications 2716.1 Analog Design Layout Revisited 2716.2 Common Centroid Design 2746.3 Interdigitation Design 2756.4 Common Centroid and Interdigitation Design 2766.5 Passive Element Design 2776.6 Resistor Element Design 2776.7 Capacitor Element Design 2836.8 Inductor Element Design 2836.9 Summary and Closing Comments 286Problems 286References 2867 Off-Chip Drivers and ESD 2887.1 Off-chip Drivers 2887.2 OCDs: MVI 2977.3 OCDs: Self-Bias Well OCD Networks 2977.4 Programmable Impedance OCD Network 3027.5 OCDs: Universal OCDs 3057.6 OCDs: Gate-Array OCD Design 3067.7 OCDs: Gate-Modulated Networks 3097.8 OCDs ESD Design: Integration of Coupling and Ballasting Techniques 3117.9 Substrate-Modulated Resistor-Ballasted MOSFET 3157.10 Summary and Closing Comments 317Problems 318References 3198 Receiver Circuits 3228.1 Receivers and ESD 3228.2 Receivers and ESD 3248.3 Receivers and Receiver Evolution 3278.4 Receiver Circuits with Pseudozero VT Half-Pass TG 3378.5 Receiver with ZVT TG 3398.6 Receiver Circuits with Bleed Transistors 3428.7 Receiver Circuits with Test Functions 3438.8 Receiver with Schmitt Trigger Feedback Network 3448.9 Bipolar Transistor Receivers 3478.10 Differential Receivers 3498.11 CMOS Differential Receiver with Analog Layout Concepts 3558.12 Summary and Closing Comments 363Problems 364References 3669 Silicon on Insulator (SOI) ESD Design 3689.1 Silicon on Insulator ESD Design Concepts 3689.2 SOI Design MOSFET with Body Contact: T-Shape Layout Style 3729.3 SOI Lateral Diode Structure 3759.4 SOI BR Elements 3809.5 Dynamic Threshold SOI MOSFET 3819.6 SOI Dual-Gate MOSFET 3849.7 SOI ESD Design: Mixed Voltage T-Shape Layout Style 3849.8 SOI ESD Design: Mixed Voltage Diode Strings 3849.9 SOI ESD Design: Double-Diode Network 3859.10 Bulk to SOI ESD Design Remapping 3879.11 SOI ESD Design in MVI Environments 3919.12 Comparison of Bulk to SOI ESD Results 3939.13 SOI ESD Design with Aluminum Interconnects 3949.14 SOI ESD Design with Copper Interconnects 3959.15 SOI ESD Design with Gate Circuitry 3979.16 SOI FinFET Structure 3999.17 Summary and Closing Comments 403Problems 403References 40510 ESD Circuits: BiCMOS 40810.1 Bipolar ESD Input Circuits 40810.2 Diode-Configured Bipolar ESD Input Circuits 41210.3 Bipolar ESD Input Circuits: Voltage-Triggered Elements 41310.4 BiCMOS Mixed Signal Designs 43710.5 Summary and Closing Comments 437Problems 437References 43811 ESD Power Clamps 44211.1 ESD Power Clamp Design Practices 44211.2 Design Synthesis of ESD Power Clamps Trigger Networks 44611.3 Design Synthesis of ESD Power Clamp: The ESD Power Clamp Shunting Element 44911.4 ESD Power Clamp Issues 45211.5 ESD Power Clamp Design 45311.6 Master/Slave ESD Power Clamp Systems 45811.7 Series-Stacked RC-Triggered ESD Power Clamps 46011.8 ESD Power Clamps: Triple-Well Series Diodes as Core Clamps 46011.9 Summary and Closing Comments 464Problems 465References 46612 Bipolar ESD Power Clamps 46812.1 Bipolar ESD Power Clamps 46812.2 Bipolar Voltage-Triggered ESD Power Clamps 46812.3 ESD Power Clamp Design Synthesis: Bipolar ESD Power Clamps 47312.4 Mixed Voltage Interface Forward-Bias Voltage and BVCEO Breakdown Synthesized Bipolar ESD Power Clamps 47612.5 Ultralow-Voltage Forward-Biased Voltage-Trigger BiCMOS ESD Power Clamp 48012.6 Bipolar ESD Power Clamps with Frequency Trigger Elements: Capacitance Triggered 48512.7 Summary and Closing Comments 485Problems 486References 48713 Silicon-Controlled Rectifier Power Clamps 48913.1 ESD Silicon-Controlled Rectifier Circuits 48913.2 Lateral Diffused MOS Circuits 49213.3 DeMOS Circuits 49613.4 Ultrahigh-Voltage LDMOS (UHV-LDMOS) Circuits 49713.5 Summary and Closing Comments 497Problems 501References 501Glossary of Terms 504Standards 509Index
Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.” Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the “ESD on Campus” program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents. Dr. Voldman is an author of the book series including ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.
ESD: Circuits and Devices 2nd Edition provides a clear picture of layout and design of digital, analog, radio frequency (RF) and power applications for protection from electrostatic discharge (ESD), electrical overstress (EOS), and latchup phenomena from a generalist perspective and design synthesis practices providing optimum solutions in advanced technologies. New features in the 2nd edition: • Expanded treatment of ESD and analog design of passive devices of resistors, capacitors, inductors, and active devices of diodes, bipolar junction transistors, MOSFETs, and FINFETs. • Increased focus on ESD power clamps for power rails for CMOS, Bipolar, and BiCMOS. • Co-synthesizing of semiconductor chip architecture and floor planning with ESD design practices for analog, and mixed signal applications. • Illustrates the influence of analog design practices on ESD design circuitry, from integration, synthesis and layout, to symmetry, matching, interdigitation, and common centroid techniques. • Increased emphasis on system-level testing conforming to IEC 61000-4-2 and IEC 61000-4-5. • Improved coverage of low-capacitance ESD, scaling of devices and oxide scaling challenges. ESD: Circuits and Devices 2nd Edition is an essential reference to ESD, circuit and semiconductor engineers and quality, reliability and analysis engineers. It is also useful for graduate and undergraduate students in electrical engineering, semiconductor sciences, microelectronics and IC design.
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