Details

Electrical Overstress (EOS)

Devices, Circuits and Systems
1. Aufl.

von: Steven H. Voldman
78,99 €
Verlag:	Wiley
Format:	EPUB
Veröffentl.:	27.08.2013
ISBN/EAN:	9781118703335
Sprache:	englisch
Anzahl Seiten:	368

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Titelbeschreibung

Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today’s modern world. Look inside for extensive coverage on: <ul> <li>Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena</li> <li>EOS sources in today’s semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures</li> <li>EOS failures in both semiconductor devices, circuits and system</li> <li>Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events)</li> <li>EOS protection on-chip design practices and how they differ from ESD protection networks and solutions</li> <li>Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment</li> <li>Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD</li> <li>EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems</li> <li>EOS testing and qualification techniques, and</li> <li>Practical off-chip ESD protection and system level solutions to provide more robust systems</li> </ul> Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.

Inhaltsverzeichnis

About the Author xvii Preface xix Acknowledgements xxiii 1 Fundamentals of Electrical Overstress 1 1.1 Electrical Overstress 2 1.1.1 The Cost of Electrical Overstress 2 1.1.2 Product Field Returns – The Percentage that is Electrical Overstress 2 1.1.3 Product Field Returns – No Defect Found versus Electrical Overstress 4 1.1.4 Product Failures – Failures in Integrated Circuits 4 1.1.5 Classification of Electrical Overstress Events 4 1.1.6 Electrical Over-Current 6 1.1.7 Electrical Over-Voltage 6 1.1.8 Electrical Over-Power 7 1.2 De-Mystifying Electrical Overstress 7 1.2.1 Electrical Overstress Events 8 1.3 Sources of Electrical Overstress 8 1.3.1 Sources of Electrical Overstress in Manufacturing Environment 8 1.3.2 Sources of Electrical Overstress in Production Environments 10 1.4 Misconceptions of Electrical Overstress 10 1.5 Minimization of Electrical Overstress Sources 11 1.6 Mitigation of Electrical Overstress 11 1.7 Signs of Electrical Overstress Damage 12 1.7.1 Signs of Electrical Overstress Damage – The Electrical Signature 12 1.7.2 Signs of Electrical Overstress Damage – The Visual Signature 13 1.8 Electrical Overstress and Electrostatic Discharge 14 1.8.1 Comparison of High and Low Current EOS versus ESD Events 15 1.8.2 Electrical Overstress and Electrostatic Discharge Differences 15 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities 17 1.8.4 Comparison of EOS versus ESDWaveforms 18 1.8.5 Comparison of EOS versus ESD Event Failure Damage 19 1.9 Electromagnetic Interference 20 1.9.1 Electrical Overstress Induced Electromagnetic Interference 20 1.10 Electromagnetic Compatibility 21 1.11 Thermal Over-Stress 21 1.11.1 Electrical Overstress and Thermal Overstress 22 1.11.2 Temperature Dependent Electrical Overstress 22 1.11.3 Electrical Overstress and Melting Temperature 23 1.12 Reliability Technology Scaling 23 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve 23 1.12.2 The Shrinking Reliability Design Box 24 1.12.3 The Shrinking Electrostatic Discharge Design Box 25 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage 25 1.13 Safe Operating Area 26 1.13.1 Electrical Safe Operating Area 26 1.13.2 Thermal Safe Operating Area 27 1.13.3 Transient Safe Operating Area 28 1.14 Summary and Closing Comments 28 References 29 2 Fundamentals of EOS Models 36 2.1 Thermal Time Constants 36 2.1.1 The Thermal Diffusion Time 37 2.1.2 The Adiabatic Regime Time Constant 38 2.1.3 The Thermal Diffusion Regime Time Constant 38 2.1.4 The Steady State Regime Time Constant 39 2.2 Pulse Event Time Constants 39 2.2.1 The ESD HBM Pulse Time Constant 39 2.2.2 The ESD MM Pulse Time Constant 39 2.2.3 The ESD Charged Device Model Pulse Time Constant 40 2.2.4 The ESD Pulse Time Constant – Transmission Line Pulse 40 2.2.5 The ESD Pulse Time Constant – Very Fast Transmission Line Pulse 41 2.2.6 The IEC 61000-4-2 Pulse Time Constant 41 2.2.7 The Cable Discharge Event Pulse Time Constant 42 2.2.8 The IEC 61000-4-5 Pulse Time Constant 42 2.3 Mathematical Methods for EOS 42 2.3.1 Mathematical Methods for EOS – Green’s Functions 42 2.3.2 Mathematical Methods for EOS – Method of Images 45 2.3.3 Mathematical Methods for EOS – Thermal Diffusion Partial Differential Equation 47 2.3.4 Mathematical Methods for EOS – Thermal Diffusion Partial Differential Equation with Variable Coefficients 48 2.3.5 Mathematical Methods for EOS – Duhamel Formulation 48 2.3.6 Mathematical Methods for EOS – Integral Transforms of the Heat Conduction Equation 53 2.4 The Spherical Model – Tasca Derivation 57 2.4.1 The Tasca Model in the ESD Time Regime 61 2.4.2 The Tasca Model in the EOS Time Regime 61 2.4.3 The Vlasov–Sinkevitch Model 62 2.5 The One-dimensional Model – Wunsch–Bell Derivation 62 2.5.1 The Wunsch–Bell Curve 66 2.5.2 The Wunsch–Bell Model in the ESD Time Regime 66 2.5.3 The Wunsch–Bell Model in the EOS Time Regime 67 2.6 The Ash Model 68 2.7 The Cylindrical Model – The Arkihpov–Astvatsaturyan–Godovosyn–Rudenko Derivation 68 2.8 The Three-dimensional Parallelepiped Model – Dwyer–Franklin–Campbell Derivation 69 2.8.1 The Dwyer–Franklin–Campbell Model in the ESD Time Regime 75 2.8.2 The Dwyer–Campbell–Franklin Model in the EOS Time Regime 75 2.9 The Resistor Model – Smith–Littau Derivation 76 2.10 Instability 79 2.10.1 Electrical Instability 79 2.10.2 Electrical Breakdown 80 2.10.3 Electrical Instability and Snapback 80 2.10.4 Thermal Instability 81 2.11 Electro-migration and Electrical Overstress 84 2.12 Summary and Closing Comments 84 References 85 3 EOS, ESD, EMI, EMC and Latchup 87 3.1 Electrical Overstress Sources 87 3.1.1 EOS Sources – Lightning 88 3.1.2 EOS Sources – Power Distribution 90 3.1.3 EOS Sources – Switches, Relays, and Coils 90 3.1.4 EOS Sources – Switch Mode Power Supplies 90 3.1.5 EOS Sources – Machinery 90 3.1.6 EOS Sources – Actuators 91 3.1.7 EOS Sources – Solenoids 91 3.1.8 EOS Sources – Servo Motors 91 3.1.9 EOS Sources – Variable Frequency Drive Motors 93 3.1.10 EOS Sources – Cables 93 3.2 EOS Failure Mechanisms 94 3.2.1 EOS Failure Mechanisms: Semiconductor Process – Application Mismatch 95 3.2.2 EOS Failure Mechanisms: Bond Wire Failure 95 3.2.3 EOS Failure Mechanisms: PCB to Chip Failures 96 3.2.4 EOS Failure Mechanisms: External Load to Chip Failures 96 3.2.5 EOS Failure Mechanisms: Reverse Insertion Failures 97 3.3 Failure Mechanism – Latchup or EOS? 97 3.3.1 Latchup versus EOS Design Window 98 3.4 Failure Mechanism – Charged Board Model or EOS? 98 3.5 Summary and Closing Comments 99 References 99 4 EOS Failure Analysis 102 4.1 Electrical Overstress Failure Analysis 102 4.1.1 EOS Failure Analysis – Information Gathering and Fact Finding 106 4.1.2 EOS Failure Analysis – Failure Analysis Report and Documentation 106 4.1.3 EOS Failure Analysis – Failure Site Localization 108 4.1.4 EOS Failure Analysis – Root Cause Analysis 108 4.1.5 EOS or ESD Failure Analysis – Can Visual Failure Analysis Tell the Difference? 108 4.2 EOS Failure Analysis – Choosing the Correct Tool 112 4.2.1 EOS Failure Analysis – Non-Destructive Methods 113 4.2.2 EOS Failure Analysis – Destructive Methods 115 4.2.3 EOS Failure Analysis – Differential Scanning Calorimetry 115 4.2.4 EOS Failure Analysis – Scanning Electron Microscope/Energy Dispersive X-ray Spectroscopy 116 4.2.5 EOS Failure Analysis – Fourier Transform Infrared Spectroscopy 116 4.2.6 EOS Failure Analysis – Ion Chromatography 117 4.2.7 EOS Failure Analysis – Optical Microscopy 117 4.2.8 EOS Failure Analysis – Scanning Electron Microscopy 118 4.2.9 EOS Failure Analysis – Transmission Electron Microscopy 118 4.2.10 EOS Failure Analysis – Emission Microscope Tool 120 4.2.11 EOS Failure Analysis – Voltage Contrast Tools 120 4.2.12 EOS Failure Analysis – IR Thermography 121 4.2.13 EOS Failure Analysis – Optical Beam Induced Resistance Change Tool 122 4.2.14 EOS Failure Analysis – IR-OBIRCH Tool 122 4.2.15 EOS Failure Analysis – Thermally Induced Voltage Alteration Tool 123 4.2.16 EOS Failure Analysis – Atomic Force Microscope Tool 124 4.2.17 EOS Failure Analysis – Super-Conducting Quantum Interference Device Microscope 125 4.2.18 EOS Failure Analysis – Picosecond Imaging Current Analysis Tool 127 4.3 Summary and Closing Comments 129 References 130 5 EOS Testing and Simulation 133 5.1 Electrostatic Discharge Testing – Component Level 133 5.1.1 ESD Testing – Human Body Model 134 5.1.2 ESD Testing – Machine Model 136 5.1.3 ESD Testing – Charged Device Model 138 5.2 Transmission Line Pulse Testing 140 5.2.1 ESD Testing – Transmission Line Pulse 140 5.2.2 ESD Testing – Very Fast Transmission Line Pulse 142 5.3 ESD Testing – System Level 143 5.3.1 ESD System Level Testing – IEC 61000-4-2 143 5.3.2 ESD Testing – Human Metal Model 144 5.3.3 ESD Testing – Charged Board Model 145 5.3.4 ESD Testing – Cable Discharge Event 146 5.4 Electrical Overstress Testing 148 5.4.1 EOS Testing – Component Level 149 5.4.2 EOS Testing – System Level 149 5.5 EOS Testing – Lightning 149 5.6 EOS Testing – IEC 61000-4-5 150 5.7 EOS Testing – Transmission Line Pulse Method and EOS 151 5.7.1 EOS Testing – Long Pulse TLP Method 152 5.7.2 EOS Testing – TLP Method, EOS and the Wunsch–Bell Model 152 5.7.3 EOS Testing – Limitations of the TLP Method for the Evaluation of EOS for Systems 152 5.7.4 EOS Testing – Electro-magnetic Pulse 153 5.8 EOS Testing – D.C. and Transient Latchup 153 5.9 EOS Testing – Scanning Methodologies 154 5.9.1 EOS Testing – Susceptibility and Vulnerability 154 5.9.2 EOS Testing – Electrostatic Discharge/Electromagnetic Compatibility Scanning 155 5.9.3 Electromagnetic Interference Emission Scanning Methodology 157 5.9.4 Radio Frequency Immunity Scanning Methodology 158 5.9.5 Resonance Scanning Methodology 158 5.9.6 Current Spreading Scanning Methodology 158 5.10 Summary and Closing Comments 161 References 161 6 EOS Robustness – Semiconductor Technologies 166 6.1 EOS and CMOS Technology 166 6.1.1 CMOS Technology – Structures 166 6.1.2 CMOS Technology – Safe Operation Area 167 6.1.3 CMOS Technology – EOS and ESD Failure Mechanisms 168 6.1.4 CMOS Technology – Protection Circuits 173 6.1.5 CMOS Technology – Silicon On Insulator 178 6.1.6 CMOS Technology – Latchup 179 6.2 EOS and RF CMOS and Bipolar Technology 180 6.2.1 RF CMOS and Bipolar Technology – Structures 180 6.2.2 RF CMOS and Bipolar Technology – Safe Operation Area 181 6.2.3 RF CMOS and Bipolar Technology – EOS and ESD Failure Mechanisms 182 6.2.4 RF CMOS and Bipolar Technology – Protection Circuits 185 6.3 EOS and LDMOS Power Technology 186 6.3.1 LDMOS Technology – Structures 187 6.3.2 LDMOS Transistors – ESD Electrical Measurements 189 6.3.3 LDMOS Technology – Safe Operation Area 190 6.3.4 LDMOS Technology – Failure Mechanisms 191 6.3.5 LDMOS Technology – Protection Circuits 193 6.3.6 LDMOS Technology – Latchup 193 6.4 Summary and Closing Comments 194 References 195 7 EOS Design – Chip Level Design and Floor Planning 196 7.1 EOS and ESD Co-Synthesis – How to Design for Both EOS and ESD 196 7.2 Product Definition Flow and Technology Evaluation 197 7.2.1 Standard Product Definition Flow 197 7.2.2 EOS Product Design Flow and Product Definition 198 7.3 EOS Product Definition Flow – Constant Reliability Scaling 199 7.4 EOS Product Definition Flow – Bottom Up Design 200 7.5 EOS Product Definition Flow – Top Down Design 200 7.6 On-Chip EOS Considerations – Bond Pad and Bond Wire Design 202 7.7 EOS Peripheral I/O Floor Planning 202 7.7.1 EOS Peripheral I/O Floor Planning – VDD-to-VSS Power Clamp Placement in Corners 203 7.7.2 EOS Peripheral I/O Floor Planning – Distributed Power Clamp Placement 204 7.7.3 EOS Peripheral I/O Floor Planning – Multi-Domain Semiconductor Chips 205 7.8 EOS Chip Power Grid Design – IEC Specification Power Grid and Interconnect Design Considerations 206 7.8.1 IEC 61000-4-2 Power Grid 207 7.8.2 ESD Power Clamp Design Synthesis – IEC 61000-4-2 Responsive ESD Power Clamps 207 7.9 Printed Circuit Board Design 209 7.9.1 System Level Board Design – Ground Design 209 7.9.2 System Card Insertion Contacts 209 7.9.3 Component and EOS Protection Device Placement 210 7.10 Summary and Closing Comments 211 References 211 8 EOS Design – Chip Level Circuit Design 213 8.1 EOS Protection Devices 213 8.2 EOS Protection Device Classification Characteristics 213 8.2.1 EOS Protection Device Classification – Voltage Suppression 214 8.2.2 EOS Protection Device – Current-Limiting Devices 215 8.3 EOS Protection Device – Directionality 216 8.3.1 EOS Protection Device – Uni-Directional 216 8.3.2 EOS Protection Device – Bi-Directional 217 8.4 EOS Protection Device Classification – I-V Characteristic Type 217 8.4.1 EOS Protection Device Classification – Positive Resistance I-V Characteristic Type 218 8.4.2 EOS Protection Device Classification – S-Type I-V Characteristic Type 219 8.5 EOS Protection Device Design Window 220 8.5.1 EOS Protection Device versus ESD Device Design Window 220 8.5.2 EOS and ESD Co-Synthesis 221 8.5.3 EOS Activates ESD Circuitry 221 8.6 EOS Protection Device – Types of Voltage Suppression Devices 222 8.6.1 EOS Protection Device – TVS Device 222 8.6.2 EOS Protection Device – Diodes 222 8.6.3 EOS Protection Device – Schottky Diodes 223 8.6.4 EOS Protection Device – Zener Diodes 223 8.6.5 EOS Protection Device – Thyristor Surge Protection Device 224 8.6.6 EOS Protection Device – Metal Oxide Varistors Device 225 8.6.7 EOS Protection Device – Gas Discharge Tube Devices 228 8.7 EOS Protection Device – Types of Current-Limiting Devices 229 8.7.1 EOS Protection Device – Current-Limiting Devices – PTC Devices 230 8.7.2 EOS Protection Device – Conductive Polymer Devices 231 8.7.3 EOS Protection Device – Current-Limiting Devices – Fuses 232 8.7.4 EOS Protection Device – Current-Limiting Devices – eFuse 234 8.7.5 EOS Protection Device – Current-Limiting Devices – Circuit Breakers 235 8.8 EOS Protection – Across Board Supply and Ground Plane Using a Transient Voltage Suppression Device and Schottky Diodes 236 8.9 EOS and ESD Protection Co-Synthesis Network 237 8.10 Co-Synthesis of EOS in Cables and PCBs 237 8.11 Summary and Closing Comments 239 References 239 9 EOS Prevention and Control 240 9.1 Controlling EOS 240 9.1.1 Controlling EOS in a Manufacturing Environment 240 9.1.2 Controlling EOS in a Production Environment 241 9.1.3 Controlling EOS in a Back End Process 242 9.2 EOS Minimization 242 9.2.1 EOS Prevention – Manufacturing Area Operation 244 9.2.2 EOS Prevention – Production Area Operation 246 9.3 EOS Minimization – Preventive Actions in the Design Process 246 9.4 EOS Prevention – EOS Guidelines and Procedures 246 9.5 EOS Prevention – Ground Testing 247 9.6 EOS Prevention – Connectivity 247 9.7 EOS Prevention – Insertion 247 9.8 EOS and Electromagnetic Interference Prevention – Printed Circuit Board Design 248 9.8.1 EOS and EMI Prevention – PCB Power Plane and Ground Design 248 9.8.2 EOS and EMI Prevention – PCB Design Guidelines – Component Selection and Placement 249 9.8.3 EOS and EMI Prevention – PCB Design Guidelines – Trace Routing and Planes 250 9.9 EOS Prevention – Desktop Boards 251 9.10 EOS Prevention – On-Board and On-Chip Design Solutions 252 9.10.1 EOS Prevention – Operational Amplifier 252 9.10.2 EOS Prevention – Low Dropout Regulators 253 9.10.3 EOS Prevention – Soft Start Over-current and Over-voltage Protection Circuitry 254 9.10.4 EOS Prevention – Power Supply EOC and EOV Protection 255 9.11 High Performance Serial Buses and EOS 257 9.11.1 High Performance Serial Buses – FireWire and EOS 257 9.11.2 High Performance Serial Buses – Peripheral Component Interconnect Express and EOS 258 9.11.3 High Performance Serial Buses – Universal Serial Bus and EOS 259 9.12 Summary and Closing Comments 259 References 259 10 EOS Design – Electronic Design Automation 263 10.1 EOS and Electronic Design Automation 263 10.2 EOS and ESD Design Rule Checking 263 10.2.1 ESD Design Rule Check 264 10.2.2 ESD Layout Versus Schematic Verification 265 10.2.3 ESD Electrical Rule Check 266 10.3 EOS Electronic Design Automation 266 10.3.1 EOS Design Rule Checking 267 10.3.2 EOS Layout Versus Schematic Verification 268 10.3.3 EOS Electrical Rule Check 269 10.3.4 EOS Programmable Electrical Rule Check 270 10.4 Printed Circuit Board Design Checking and Verification 270 10.5 EOS and Latchup Design Rule Checking 273 10.5.1 Latchup Design Rule Check 273 10.5.2 Latchup Electrical Rule Check 277 10.6 Summary and Closing Comments 282 References 282 11 EOS Program Management 285 11.1 EOS Audits and Manufacturing Control 285 11.2 Controlling EOS in the Production Process 287 11.3 EOS and Assembly Plant Corrective Actions 287 11.4 EOS Audits – From Manufacturing to Assembly Control 288 11.5 EOS Program – Weekly, Monthly, Quarterly, to Annual Audits 288 11.6 EOS and ESD Design Release 289 11.6.1 EOS Design Release Process 290 11.6.2 ESD Cookbook 290 11.6.3 EOS Cookbook 293 11.6.4 EOS Checklists 295 11.6.5 EOS Design Reviews 297 11.7 EOS Design, Testing and Qualification 297 11.8 Summary and Closing Comments 298 References 298 12 Electrical Overstress in Future Technologies 301 12.1 EOS Future Implications for Future Technologies 301 12.2 EOS in Advanced CMOS Technology 302 12.2.1 EOS in FinFET Technology 303 12.2.2 EOS and Circuit Design 303 12.3 EOS Implications in 2.5-D and 3-D Systems 304 12.3.1 EOS Implications in 2.5-D Systems 305 12.3.2 EOS and Silicon Interposers 305 12.3.3 EOS and Through Silicon Vias 307 12.3.4 EOS Implications in 3-D Systems 309 12.4 EOS and Magnetic Recording 309 12.4.1 EOS and Magneto-Resistors 309 12.4.2 EOS and Giant Magneto-Resistors 311 12.4.3 EOS and Tunneling Magneto-Resistors 312 12.5 EOS and Micro-Machines 312 12.5.1 Micro-Electromechanical Devices 312 12.5.2 ESD Concerns in MEM Devices 313 12.5.3 Micro-Motors 314 12.5.4 ESD Concerns in Micro-Motors 314 12.6 EOS and RF MEMs 316 12.7 EOS Implications for Nano-Structures 318 12.7.1 EOS and Phase Change Memory 318 12.7.2 EOS and Graphene 320 12.7.3 EOS and Carbon Nanotubes 320 12.8 Summary and Closing Comments 322 References 322 Appendix A: Glossary of Terms 329 Appendix B: Standards 335 Index 339

Autorenportrait

Steven H . Voldman , IEEE Fellow, Vermont, USA

Back cover copy

Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This book teaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today’s modern world. Look inside for extensive coverage on: <ul> <li>Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA),to physical models for EOS phenomena</li> <li>EOS sources in today’s semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures</li> <li>EOS failures in both semiconductor devices, circuits and systems</li> <li>Discussion of how to distinguish between EOS events and electrostatic discharge (ESD) events, such as the human body model (HBM), charged device model (CDM), cable discharge events (CDM),charged board events (CBE), to system level IEC 61000-4-2 test events</li> <li>EOS protection on-chip design practices and how they differ from ESD protection networks and solutions</li> <li>Discussion of EOS system level concerns in printed circuit boards (PCB) and manufacturing equipment</li> <li>Examples of EOS issues in state-of-the-art digital, analog and power technologies, including CMOS, LDMOS, and BCD</li> <li>EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems</li> <li>EOS testing and qualification techniques</li> <li>Practical off-chip ESD protection and system level solutions to provide more robust systems</li> </ul> Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author’s series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era.