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Preface xiii <p><b>1 The Magic of Delta-Sigma Modulation 1</b></p> <p>1.1 The Need for Oversampling Converters 1</p> <p>1.2 Nyquist and Oversampling Conversion by Example 3</p> <p>1.3 Higher-Order Single-Stage Noise-Shaping Modulators 11</p> <p>1.4 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 12</p> <p>1.5 Mismatch Shaping in Multi-Bit Delta-Sigma Modulators 14</p> <p>1.6 Continuous-Time Delta-Sigma Modulation 15</p> <p>1.7 Bandpass Delta-Sigma Modulators 17</p> <p>1.8 Incremental Delta-Sigma Converters 18</p> <p>1.9 Delta-Sigma Digital-to-Analog Converters 18</p> <p>1.10 Decimation and Interpolation 19</p> <p>1.11 Specifications and Figures of Merit 19</p> <p>1.12 Early History, Performance, and Architectural Trends 21</p> <p>References 25</p> <p><b>2 Sampling, Oversampling, and Noise-Shaping 27</b></p> <p>2.1 A Review of Sampling 28</p> <p>2.2 Quantization 30</p> <p>2.3 Quantization Noise Reduction by Oversampling 39</p> <p>2.4 Noise-Shaping 42</p> <p>2.5 Nonlinear Aspects of the First-Order Delta-Sigma Modulator 52</p> <p>2.6 MOD1 with DC Excitation 54</p> <p>2.7 Alternative Architectures: The Error-Feedback Structure 60</p> <p>2.8 The Road Ahead 60</p> <p>References 61</p> <p><b>3 Second-Order Delta-Sigma Modulation 63</b></p> <p>3.1 Simulation of MOD2 67</p> <p>3.2 Nonlinear Effects in MOD2 70</p> <p>3.3 Stability of MOD2 73</p> <p>3.4 Alternative Second-Order Modulator Structures 77</p> <p>3.5 Generalized Second-Order Structures 80</p> <p>3.6 Conclusions 82</p> <p>References 82</p> <p><b>4 High-Order Delta-Sigma Modulators 83</b></p> <p>4.1 Signal-Dependent Stability of Delta-Sigma Modulators 85</p> <p>4.2 Improving MSA in High-Order Delta-Sigma Converters 92</p> <p>4.3 Systematic NTF Design 95</p> <p>4.4 Noise Transfer Functions with Optimally Spread Zeros 97</p> <p>4.5 Fundamental Aspects of Noise Transfer Functions 98</p> <p>4.6 High-Order Single-Bit Delta-Sigma Data Converters 100</p> <p>4.7 Loop Filter Topologies for Discrete-Time Delta-Sigma Converters 104</p> <p>4.8 State-Space Description of Delta-Sigma Loops 114</p> <p>4.9 Conclusions 115</p> <p>References 115</p> <p><b>5 Multi-Stage and Multi-Quantizer Delta-Sigma Modulators 117</b></p> <p>5.1 Multi-Stage Modulators 117</p> <p>5.2 Cascade (MASH) Modulators 120</p> <p>5.3 Noise Leakage in Cascade Modulators 123</p> <p>5.4 The Sturdy-MASH Architecture 126</p> <p>5.5 Noise-Coupled Architectures 128</p> <p>5.6 Cross-Coupled Architectures 131</p> <p>5.7 Conclusions 131</p> <p>References 133</p> <p><b>6 Mismatch-Shaping 135</b></p> <p>6.1 The Mismatch Problem 135</p> <p>6.2 Random Selection and Rotation 136</p> <p>6.3 Implementation of Rotation 141</p> <p>6.4 Alternative Mismatch-Shaping Topologies 145</p> <p>6.5 High-Order Mismatch-Shaping 151</p> <p>6.6 Generalizations 156</p> <p>6.7 Transition-Error Shaping 158</p> <p>6.8 Conclusions 162</p> <p>References 162</p> <p><b>7 Circuit Design for Discrete-Time Delta-Sigma ADCs 165</b></p> <p>7.1 SCMOD2: A Second-Order Switched-Capacitor ADC 165</p> <p>7.2 High-Level Design 166</p> <p>7.3 Switched-Capacitor Integrator 168</p> <p>7.4 Capacitor Sizing 174</p> <p>7.5 Initial Verification 176</p> <p>7.6 Amplifier Design 178</p> <p>7.7 Intermediate Verification 186</p> <p>7.8 Switch Design 191</p> <p>7.9 Comparator Design 191</p> <p>7.10 Clocking 195</p> <p>7.11 Full-System Verification 197</p> <p>7.12 High-Order Modulators 201</p> <p>7.13 Multi-Bit Quantization 203</p> <p>7.14 Switch Design Revisited 207</p> <p>7.15 Double Sampling 209</p> <p>7.16 Gain-Boosting and Gain-Squaring 211</p> <p>7.17 Split-Steering and Amplifier Stacking 212</p> <p>7.18 Noise in Switched-Capacitor Circuits 217</p> <p>7.19 Conclusions 221</p> <p>References 221</p> <p><b>8 Continuous-Time Delta-Sigma Modulation 223</b></p> <p>8.1 CT-MOD1 224</p> <p>8.2 STF of CT-MOD1 230</p> <p>8.3 Second-Order Continuous-Time Delta-Sigma Modulation 234</p> <p>8.4 High-Order Continuous-Time Delta-Sigma Modulators 239</p> <p>8.5 Loop-Filter Topologies 246</p> <p>8.6 Continuous-Time Delta-Sigma Modulators with Complex NTF Zeros 249</p> <p>8.7 Modeling of Continuous-Time Delta-Sigma Modulators for Simulation 250</p> <p>8.8 Dynamic-Range Scaling 253</p> <p>8.9 Design Example 255</p> <p>8.10 Conclusions 258</p> <p>References 258</p> <p><b>9 Nonidealities in Continuous-Time Delta-Sigma Modulators 259</b></p> <p>9.1 Excess Loop Delay 259</p> <p>9.2 Time-Constant Variations of the Loop Filter 271</p> <p>9.3 Clock Jitter in Delta-Sigma Modulators 273</p> <p>9.4 Addressing Clock Jitter in Continuous-Time Delta-Sigma Modulators 285</p> <p>9.5 Mitigating Clock Jitter Using FIR Feedback 287</p> <p>9.6 Comparator Metastability 293</p> <p>9.7 Conclusions 298</p> <p>References 298</p> <p><b>10 Circuit Design for Continuous-Time Delta-Sigma Modulators 301</b></p> <p>10.1 Integrators 302</p> <p>10.2 The Miller-Compensated OTA-RC Integrator 305</p> <p>10.3 The Feedforward-Compensated OTA-RC Integrator 306</p> <p>10.4 Stability of Feedforward Amplifiers 309</p> <p>10.5 Device Noise in Continuous-Time Delta-Sigma Modulators 312</p> <p>10.6 ADC Design 316</p> <p>10.7 Feedback DAC Design 320</p> <p>10.8 Systematic Design Centering 331</p> <p>10.9 Loop-Filter Nonlinearities in Continuous-Time Delta-Sigma Modulators 338</p> <p>10.10 Case Study of a 16-Bit Audio Continuous-Time Delta-Sigma Modulator346</p> <p>10.11 Measurement Results 358</p> <p>10.12 Summary 359</p> <p>References 360</p> <p><b>11 Bandpass and Quadrature Delta-Sigma Modulation 363</b></p> <p>11.1 The Need for Bandpass Conversion 363</p> <p>11.2 System Overview 366</p> <p>11.3 Bandpass NTFs 367</p> <p>11.4 Architectures for Bandpass Delta-Sigma Modulators 372</p> <p>11.5 Bandpass Modulator Example 380</p> <p>11.6 Quadrature Signals 391</p> <p>11.7 Quadrature Modulation 396</p> <p>11.8 Polyphase Signal Processing 402</p> <p>11.9 Conclusions 404</p> <p>References 405</p> <p><b>12 Incremental Analog-to-Digital Converters 407</b></p> <p>12.1 Motivation and Trade-Offs 407</p> <p>12.2 Analysis and Design of Single-Stage IADCs 408</p> <p>12.3 Digital Filter Design for Single-Stage IADCs 411</p> <p>12.4 Multiple-Stage IADCs and Extended Counting ADCs 415</p> <p>12.5 IADC Design Examples 416</p> <p>12.6 Conclusions 422</p> <p>References 423</p> <p><b>13 Delta-Sigma DACs 425</b></p> <p>13.1 System Architectures for Delta-Sigma DACs 425</p> <p>13.2 Loop Configurations for Delta-Sigma DACs 427</p> <p>13.3 Delta-Sigma DACs Using Multi-Bit Internal DACs 431</p> <p>13.4 Interpolation Filtering for Delta-Sigma DACs 438</p> <p>13.5 Analog Post-Filters for Delta-Sigma DACs 441</p> <p>13.6 Conclusions 449</p> <p>References 449</p> <p><b>14 Interpolation and Decimation Filters 451</b></p> <p>14.1 Interpolation Filtering 452</p> <p>14.2 Example Interpolation Filter 456</p> <p>14.3 Decimation Filtering 461</p> <p>14.4 Example Decimation Filter 463</p> <p>14.5 Halfband Filters 467</p> <p>14.5.1 Saramäki Halfband Filter 469</p> <p>14.6 Decimation for Bandpass Delta-Sigma ADCs 471</p> <p>14.7 Fractional Rate Conversion 472</p> <p>14.8 Summary 480</p> <p>References 480</p> <p><b>A Spectral Estimation 483</b></p> <p>A.1 Windowing 484</p> <p>A.2 Scaling and Noise Bandwidth 488</p> <p>A.3 Averaging 491</p> <p>A.4 An Example 493</p> <p>A.5 Mathematical Background 495</p> <p>References 498</p> <p><b>B The Delta-Sigma Toolbox 499</b></p> <p><b>C Linear Periodically Time-Varying Systems 539</b></p> <p>C.1 Linearity and Time (In)variance 539</p> <p>C.2 Linear Time-Varying Systems 541</p> <p>C.3 Linear Periodically Time-Varying (LPTV) Systems 543</p> <p>C.4 LPTV Systems with Sampled Outputs 547</p> <p>References 559</p> <p>Index 561</p>

<p><b>Shanthi Pavan</b> is a Professor of electrical engineering at the Indian Institute of Technology, India, and has been the Editor-In-Chief of the IEEE Transactions on Circuits and Systems, and a Distinguished Lecturer of the IEEE Solid State Circuits Society.  He is a Fellow of the Indian National Academy of Engineering.</p> <p><b>Richard Schreier</b> was a Division Fellow in Analog Devices Inc. and an Adjunct Professor at the University of Toronto, Canada, when he retired in 2016. From 1991-1997 he was a Professor at Oregon State University.He was named an IEEE Fellow in 2015.</p> <p><b>Gabor Temes</b> is a Distinguished Professor Emeritus of the University of California, and Professor in the School of Electrical Engineering and Computer Science at Oregon State University, USA.  He is an IEEE Life Fellow and a member of the US National Academy of Engineering.</p>

<p><b>This new edition introduces novel analysis and design techniques for delta-sigma (ΔΣ) converters in physical and conceptual terms, and includes new chapters that explore developments in the field over the last decade.</b></p> <p>This book explains the principles and operation of delta-sigma analog-to-digital converters (ADCs) in physical and conceptual terms in accordance with the most recent developments in the field. The interest of ΔΣ converter designers has shifted significantly over the past decade, due to many new applications for data converters at the far ends of the frequency spectrum. Continuous-time delta-sigma A/D converters with GHz clocks, of both lowpass and bandpass types, are required for wireless applications. At the other extreme, multiplexed ADCs with very narrow (sometimes 10 Hz wide) signal bandwidths, but very high accuracy are needed in the interfaces of biomedical and environmental sensors. To reflect the changing needs of designers, the second edition includes significant new material on both theory and design techniques. New text has been added, that:</p> <ul> <li>Includes insight on MASH architectures, digital-to-analog converter (DAC) mismatch and mismatch shaping</li> <li>Gives information and intuition behind several new topics,  including continuous-time ΔΣ ADCs, circuit design for both continuous-time and discrete-time ΔΣ ADCs, decimation and interpolation filters, and incremental ADCs</li> <li>Provides information on practical design issues for industry professionals.</li> </ul>

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