Details

Time-Predictable Architectures


Time-Predictable Architectures


1. Aufl.

von: Christine Rochange, Pascal Sainrat, Sascha Uhrig

139,99 €

Verlag: Wiley
Format: PDF
Veröffentl.: 17.01.2014
ISBN/EAN: 9781118790137
Sprache: englisch
Anzahl Seiten: 192

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Beschreibungen

<p>Building computers that can be used to design embedded real-time systems is the subject of this title. Real-time embedded software requires increasingly higher performances. The authors therefore consider processors that implement advanced mechanisms such as pipelining, out-of-order execution, branch prediction, cache memories, multi-threading, multicorearchitectures, etc. The authors of this book investigate the timepredictability of such schemes.</p>
<p>PREFACE ix</p> <p><b>CHAPTER 1. REAL-TIME SYSTEMS AND TIME PREDICTABILITY 1</b></p> <p>1.1. Real-time systems 1</p> <p>1.1.1. Introduction 1</p> <p>1.1.2. Soft, firm and hard real-time systems 4</p> <p>1.1.3. Safety standards 6</p> <p>1.1.4. Examples 7</p> <p>1.2. Time predictability 15</p> <p>1.3. Book outline 16</p> <p><b>CHAPTER 2. TIMING ANALYSIS OF REAL-TIME SYSTEMS 19</b></p> <p>2.1. Real-time task scheduling 19</p> <p>2.1.1. Task model 19</p> <p>2.1.2. Objectives of task scheduling algorithms 20</p> <p>2.1.3. Mono-processor scheduling for periodic tasks 21</p> <p>2.1.4. Scheduling sporadic and aperiodic tasks 23</p> <p>2.1.5. Multiprocessor scheduling for periodic tasks 23</p> <p>2.2. Task-level analysis 24</p> <p>2.2.1. Flow analysis: identifying possible paths 25</p> <p>2.2.2. Low-level analysis: determining partial execution times 27</p> <p>2.2.3. WCET computation 29</p> <p>2.2.4. WCET analysis tools 32</p> <p>2.2.5. Alternative approaches to WCET analysis 32</p> <p>2.2.6. Time composability 35</p> <p><b>CHAPTER 3. CURRENT PROCESSOR ARCHITECTURES  37</b></p> <p>3.1. Pipelining 37</p> <p>3.1.1. Pipeline effects 38</p> <p>3.1.2. Modeling for timing analysis 41</p> <p>3.1.3. Recommendations for predictability 49</p> <p>3.2. Superscalar architectures 49</p> <p>3.2.1. In-order execution 50</p> <p>3.2.2. Out-of-order execution 52</p> <p>3.2.3. Modeling for timing analysis 55</p> <p>3.2.4. Recommendations for predictability 56</p> <p>3.3. Multithreading 57</p> <p>3.3.1. Time-predictability issues raised by multithreading 58</p> <p>3.3.2. Time-predictable example architectures 60</p> <p>3.4. Branch prediction 62</p> <p>3.4.1. State-of-the-art branch prediction 62</p> <p>3.4.2. Branch prediction in real-time systems 64</p> <p>3.4.3. Approaches to branch prediction modeling 65</p> <p><b>CHAPTER 4. MEMORY HIERARCHY 69</b></p> <p>4.1. Caches 71</p> <p>4.1.1. Organization of cache memories 71</p> <p>4.1.2. Static analysis of the behavior of caches 74</p> <p>4.1.3. Recommendations for timing predictability 81</p> <p>4.2. Scratchpad memories 87</p> <p>4.2.1. Scratchpad RAM 87</p> <p>4.2.2. Data scratchpad 87</p> <p>4.2.3. Instruction scratchpad 88</p> <p>4.3. External memories 93</p> <p>4.3.1. Static RAM 93</p> <p>4.3.2. Dynamic RAM 97</p> <p>4.3.3. Flash memory 103</p> <p><b>CHAPTER 5. MULTICORES 105</b></p> <p>5.1. Impact of resource sharing on time predictability 105</p> <p>5.2. Timing analysis for multicores 106</p> <p>5.2.1. Analysis of temporal/bandwidth sharing 107</p> <p>5.2.2. Analysis of spatial sharing 110</p> <p>5.3. Local caches 111</p> <p>5.3.1. Coherence techniques 112</p> <p>5.3.2. Discussion on timing analyzability 115</p> <p>5.4. Conclusion 121</p> <p>5.5. Time-predictable architectures 121</p> <p>5.5.1. Uncached accesses to shared data 121</p> <p>5.5.2. On-demand coherent cache 123</p> <p><b>CHAPTER 6. EXAMPLE ARCHITECTURES 127</b></p> <p>6.1. The multithreaded processor Komodo 127</p> <p>6.1.1. The Komodo architecture 128</p> <p>6.1.2. Integrated thread scheduling 130</p> <p>6.1.3. Guaranteed percentage scheduling 131</p> <p>6.1.4. The jamuth IP core 132</p> <p>6.1.5. Conclusion 134</p> <p>6.2. The JOP architecture 134</p> <p>6.2.1. Conclusion 136</p> <p>6.3. The PRET architecture 136</p> <p>6.3.1. PRET pipeline architecture 136</p> <p>6.3.2. Instruction set extension 137</p> <p>6.3.3. DDR2 memory controller 137</p> <p>6.3.4. Conclusion 138</p> <p>6.4. The multi-issue CarCore processor 138</p> <p>6.4.1. The CarCore architecture 139</p> <p>6.4.2. Layered thread scheduling 140</p> <p>6.4.3. CarCore thread scheduling algorithms 142</p> <p>6.4.4. Conclusion 146</p> <p>6.5. The MERASA multicore processor 146</p> <p>6.5.1. The MERASA architecture 147</p> <p>6.5.2. The MERASA processor core 148</p> <p>6.5.3. Interconnection bus 149</p> <p>6.5.4. Memory hierarchy 149</p> <p>6.5.5. Conclusion 150</p> <p>6.6. The T-CREST multicore processor 151</p> <p>6.6.1. The Patmos processor core 151</p> <p>6.6.2. The T-CREST interconnect 152</p> <p>6.6.3. Conclusion 153</p> <p>6.7. The parMERASA manycore processor 154</p> <p>6.7.1. System overview 154</p> <p>6.7.2. Memory hierarchy 155</p> <p>6.7.3. Communication infrastructure 157</p> <p>6.7.4. Peripheral devices and interrupt system 159</p> <p>6.7.5. Conclusion 161</p> <p>BIBLIOGRAPHY 163</p> <p>INDEX 179</p>
<p><strong>Christine Rochange</strong> is Associate professor at Université Paul Sabatier (IRIT), Toulouse, France. <p><strong>Pascal Sainrat</strong>, Université Paul Sabatier, (IRIT), Toulouse, France. <p><strong>Sascha Uhrig</strong>, University of Dortmund, Germany.

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