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<p>Preface xiii</p> <p>Book Layout xv</p> <p>Acknowledgments xvii</p> <p><b>1 Introduction to Real-Time Embedded Systems 1</b></p> <p>1.1 Real-Time Embedded Systems 1</p> <p>1.2 Example: Automobile Antilock Braking System 3</p> <p>1.2.1 Slip Rate and Brake Force 3</p> <p>1.2.2 ABS Components 4</p> <p>1.2.2.1 Sensors 4</p> <p>1.2.2.2 Valves and Pumps 5</p> <p>1.2.2.3 Electrical Control Unit 7</p> <p>1.2.3 ABS Control 8</p> <p>1.3 Real-Time Embedded System Characteristics 10</p> <p>1.3.1 System Structure 10</p> <p>1.3.2 Real-Time Response 10</p> <p>1.3.3 Highly Constrained Environments 11</p> <p>1.3.4 Concurrency 12</p> <p>1.3.5 Predictability 12</p> <p>1.3.6 Safety and Reliability 13</p> <p>1.4 Hard and Soft Real-Time Embedded Systems 13</p> <p>Exercises 14</p> <p>Suggestions for Reading 15</p> <p>References 15</p> <p><b>2 Hardware Components 17</b></p> <p>2.1 Processors 17</p> <p>2.1.1 Microprocessors 17</p> <p>2.1.2 Microcontrollers 19</p> <p>2.1.3 Application-Specific Integrated Circuits (ASICs) 19</p> <p>2.1.4 Field-Programmable Gate Arrays (FPGAs) 19</p> <p>2.1.5 Digital Signal Processors (DSPs) 20</p> <p>2.1.6 Application-Specific Instruction Set Processors (ASIPs) 20</p> <p>2.1.7 Multicore Processors 20</p> <p>2.1.8 Von Neumann Architecture and Harvard Architecture 21</p> <p>2.1.9 Complex Instruction Set Computing and Reduced Instruction Set Computing 22</p> <p>2.2 Memory and Cache 23</p> <p>2.2.1 Read-Only Memory (ROM) 23</p> <p>2.2.2 Random-Access Memory (RAM) 24</p> <p>2.2.3 Cache Memory 24</p> <p>2.3 I/O Interfaces 26</p> <p>2.4 Sensors and Actuators 27</p> <p>2.5 Timers and Counters 29</p> <p>Exercises 30</p> <p>Suggestions for Reading 31</p> <p>References 31</p> <p><b>3 Real-Time Operating Systems 33</b></p> <p>3.1 Main Functions of General-Purpose Operating Systems 33</p> <p>3.1.1 Process Management 34</p> <p>3.1.2 Memory Management 36</p> <p>3.1.3 Interrupts Management 39</p> <p>3.1.4 Multitasking 39</p> <p>3.1.5 File System Management 39</p> <p>3.1.6 I/O Management 41</p> <p>3.2 Characteristics of RTOS Kernels 42</p> <p>3.2.1 Clocks and Timers 42</p> <p>3.2.2 Priority Scheduling 44</p> <p>3.2.3 Intertask Communication and Resource Sharing 45</p> <p>3.2.3.1 Real-Time Signals 45</p> <p>3.2.3.2 Semaphores 46</p> <p>3.2.3.3 Message Passing 46</p> <p>3.2.3.4 Shared Memory 46</p> <p>3.2.4 Asynchronous I/O 47</p> <p>3.2.5 Memory Locking 47</p> <p>3.3 RTOS Examples 48</p> <p>3.3.1 LynxOS 48</p> <p>3.3.2 OSE 49</p> <p>3.3.3 QNX 49</p> <p>3.3.4 VxWorks 49</p> <p>3.3.5 Windows Embedded Compact 50</p> <p>Exercises 50</p> <p>Suggestions for Reading 52</p> <p>References 52</p> <p><b>4 Task Scheduling 53</b></p> <p>4.1 Tasks 53</p> <p>4.1.1 Task Specification 54</p> <p>4.1.2 Task States 56</p> <p>4.1.3 Precedence Constraints 58</p> <p>4.1.4 Task Assignment and Scheduling 59</p> <p>4.2 Clock-Driven Scheduling 59</p> <p>4.2.1 Structured Clock-Driven Scheduling 62</p> <p>4.2.1.1 Frames 62</p> <p>4.2.1.2 Task Slicing 65</p> <p>4.2.2 Scheduling Aperiodic Tasks 66</p> <p>4.2.3 Scheduling Sporadic Tasks 68</p> <p>4.3 Round-Robin Approach 69</p> <p>4.4 Priority-Driven Scheduling Algorithms 70</p> <p>4.4.1 Fixed-Priority Algorithms 70</p> <p>4.4.1.1 Schedulability Test Based on Time Demand Analysis 72</p> <p>4.4.1.2 Deadline-Monotonic Algorithm 76</p> <p>4.4.2 Dynamic-Priority Algorithms 76</p> <p>4.4.2.1 Earliest-Deadline-First (EDF) Algorithm 76</p> <p>4.4.2.2 Optimality of EDF 78</p> <p>4.4.3 Priority-Driven Scheduling of Aperiodic and Sporadic Tasks 82</p> <p>4.4.3.1 Scheduling of Aperiodic Tasks 82</p> <p>4.4.3.2 Scheduling of Sporadic Tasks 85</p> <p>4.4.4 Practical Factors 85</p> <p>4.4.4.1 Nonpreemptivity 85</p> <p>4.4.4.2 Self-Suspension 86</p> <p>4.4.4.3 Context Switches 87</p> <p>4.4.4.4 Schedulability Test 87</p> <p>4.5 Task Assignment 89</p> <p>4.5.1 Bin-Packing Algorithms 89</p> <p>4.5.1.1 First-Fit Algorithm 90</p> <p>4.5.1.2 First-Fit Decreasing Algorithm 91</p> <p>4.5.1.3 Rate-Monotonic First-Fit (RMFF) Algorithm 91</p> <p>4.5.2 Assignment with Communication Cost 92</p> <p>Exercises 94</p> <p>Suggestions for Reading 97</p> <p>References 97</p> <p><b>5 Resource Sharing and Access Control 99</b></p> <p>5.1 Resource Sharing 99</p> <p>5.1.1 Resource Operation 100</p> <p>5.1.2 Resource Requirement Specification 100</p> <p>5.1.3 Priority Inversion and Deadlocks 101</p> <p>5.1.4 Resource Access Control 103</p> <p>5.2 Nonpreemptive Critical Section Protocol 103</p> <p>5.3 Priority Inheritance Protocol 106</p> <p>5.3.1 Rules of Priority Inheritance Protocol 106</p> <p>5.3.2 Properties of Priority Inheritance Protocol 109</p> <p>5.4 Priority Ceiling Protocol 111</p> <p>5.4.1 Rules of Priority Ceiling Protocol 112</p> <p>5.4.2 Properties of Priority Ceiling Protocol 114</p> <p>5.4.3 Worst-Case Blocking Time 116</p> <p>5.5 Stack-Sharing Priority Ceiling Protocol 119</p> <p>5.5.1 Rules of Stack-Sharing Priority Ceiling Protocol 119</p> <p>5.5.2 Properties of Stack-Sharing Priority Ceiling Protocol 121</p> <p>Exercises 122</p> <p>Suggestion for Reading 125</p> <p>References 125</p> <p><b>6 Concurrent Programming 127</b></p> <p>6.1 Introduction 127</p> <p>6.2 POSIX Threads 128</p> <p>6.3 Synchronization Primitives 133</p> <p>6.3.1 Race Conditions and Critical Sections 133</p> <p>6.3.2 Mutex 134</p> <p>6.3.3 Condition Variables 137</p> <p>6.3.4 Semaphores 142</p> <p>6.4 Communication among Tasks 148</p> <p>6.4.1 Message Queues 149</p> <p>6.4.2 Shared Memory 155</p> <p>6.4.3 Shared Memory Protection 157</p> <p>6.5 Real-Time Facilities 162</p> <p>6.5.1 Real-Time Signals 162</p> <p>6.5.1.1 Blocking Signals 163</p> <p>6.5.1.2 Dealing with Signals 164</p> <p>6.5.2 Timers 165</p> <p>6.5.3 Implement Periodic Tasks 169</p> <p>6.5.3.1 Using sleep() Function 169</p> <p>6.5.3.2 Using Timers 172</p> <p>6.5.4 Implement an Application with Multiple Periodic Tasks 173</p> <p>Exercises 173</p> <p>Suggestions for Reading 177</p> <p>References 177</p> <p><b>7 Finite-State Machines 179</b></p> <p>7.1 Finite State Machine Basics 179</p> <p>7.2 Deterministic Finite Automation (DFA) 181</p> <p>7.2.1 Moore Machines 182</p> <p>7.2.2 Mealy Machines 184</p> <p>7.3 Nondeterministic Finite Automation 188</p> <p>7.4 Programming Finite-State Machines 188</p> <p>Exercises 191</p> <p>Suggestions for Reading 194</p> <p>References 195</p> <p><b>8 UML State Machines 197</b></p> <p>8.1 States 198</p> <p>8.2 Transitions 200</p> <p>8.3 Events 201</p> <p>8.4 Composite States 202</p> <p>8.4.1 Hierarchy 203</p> <p>8.4.2 Orthogonality 205</p> <p>8.4.3 Submachine States 206</p> <p>8.5 Pseudostates 206</p> <p>8.5.1 History Pseudostates 206</p> <p>8.5.2 Entry and Exit Points 208</p> <p>8.5.3 Fork and Join Pseudostates 210</p> <p>8.5.4 Terminate Pseudostates 210</p> <p>8.6 UML State Machine of Antilock Braking System 211</p> <p>Exercises 215</p> <p>Suggestions for Reading 217</p> <p>References 217</p> <p><b>9 Timed Petri Nets 219</b></p> <p>9.1 Petri Net Definition 219</p> <p>9.1.1 Transition Firing 221</p> <p>9.1.2 Modeling Power 222</p> <p>9.2 Petri Net Properties 225</p> <p>9.2.1 Behavioral Properties 225</p> <p>9.2.1.1 Reachability 225</p> <p>9.2.1.2 ;; Markings 226</p> <p>9.2.1.3 Reachability Analysis Algorithm 227</p> <p>9.2.1.4 Boundedness and Safeness 229</p> <p>9.2.1.5 Liveness 229</p> <p>9.2.2 Structural Properties 230</p> <p>9.2.2.1 T-Invariants and S-Invariants 230</p> <p>9.2.2.2 Siphons and Traps 233</p> <p>9.3 Timed Petri Nets 234</p> <p>9.3.1 Deterministic Timed Petri Nets 234</p> <p>9.3.1.1 Performance Evaluation Based on DTPNs 237</p> <p>9.3.2 Time Petri Nets 240</p> <p>9.3.2.1 States in a Time Petri Net 241</p> <p>9.3.2.2 Enabling and Firing Conditions of Transitions 242</p> <p>9.3.2.3 Firing Rules 243</p> <p>Exercises 244</p> <p>Suggestions for Reading 250</p> <p>References 251</p> <p><b>10 Model Checking 253</b></p> <p>10.1 Introduction to Model Checking 253</p> <p>10.2 Temporal Logic 254</p> <p>10.2.1 Linear Temporal Logic 256</p> <p>10.2.1.1 Syntax of LTL 256</p> <p>10.2.1.2 Parse Trees for LTL Formulas 257</p> <p>10.2.1.3 Semantics of LTL 258</p> <p>10.2.1.4 Equivalencies of LTL Formulas 262</p> <p>10.2.1.5 System Property Specification 263</p> <p>10.2.2 Computation Tree logic 264</p> <p>10.2.2.1 Syntax of CTL 264</p> <p>10.2.2.2 Semantics of CTL 265</p> <p>10.2.2.3 Equivalencies of CTL Formulas 268</p> <p>10.2.3 LTL versus CTL 268</p> <p>10.3 The NuSMV Model Checking Tool 269</p> <p>10.3.1 Description Language 269</p> <p>10.3.1.1 Single-Module SMV Program 269</p> <p>10.3.1.2 Multimodule SMV Program 271</p> <p>10.3.1.3 Asynchronous Systems 273</p> <p>10.3.2 Specifications 274</p> <p>10.3.3 Running NuSMV 275</p> <p>10.4 Real-Time Computation Tree Logic 279</p> <p>Exercises 285</p> <p>Suggestions for Reading 290</p> <p>References 290</p> <p><b>11 Practical Issues 293</b></p> <p>11.1 Software Reliability 293</p> <p>11.1.1 Software Faults 293</p> <p>11.1.2 ReliabilityMeasurement 294</p> <p>11.1.3 Improving Software Reliability 295</p> <p>11.1.3.1 Fault Avoidance 295</p> <p>11.1.3.2 Fault Removal 295</p> <p>11.1.3.3 Fault Tolerance 295</p> <p>11.1.3.4 Fault Recovery 296</p> <p>11.2 Software Aging and Rejuvenation 296</p> <p>11.3 Security 297</p> <p>11.3.1 Challenges 297</p> <p>11.3.2 Common Vulnerabilities 298</p> <p>11.3.3 Secure Software Design 299</p> <p>11.4 Safety 300</p> <p>11.5 Power Conservation 301</p> <p>Suggestions for Reading 302</p> <p>References 302</p> <p>Index 305</p>

<p> <strong>Jiacun Wang Ph.D. </strong>is a Professor of Software Engineering at Monmouth University, NJ, USA. He is a former member of the scientific staff at Nortel Networks where he worked on embedded software for mobility management of 3G telecommunication systems. He is the author of <em>Timed Petri Nets: Theory and Application</em> (Kluwer 1998) and editor of <em>Handbook of Finite State Based Models and Applications</em> (CRC 2012). He is a senior member of IEEE.

<p> <b>Offering comprehensive coverage of the convergence of real-time embedded systems scheduling, resource access control, software design and development, and high-level system modeling, analysis and verification</b> <p>Following an introductory overview, Dr. Wang delves into the specifics of hardware components, including processors, memory, I/O devices and architectures, communication structures, peripherals, and characteristics of real-time operating systems. Later chapters are dedicated to real-time task scheduling algorithms and resource access control policies, as well as priority-inversion control and deadlock avoidance. Concurrent system programming and POSIX programming for real-time systems are covered, as are finite state machines and Time Petri nets. Of special interest to software engineers will be the chapter devoted to model checking, in which the author discusses temporal logic and the NuSMV model checking tool, as well as a chapter treating real-time software design with UML. The final portion of the book explores practical issues of software reliability, aging, rejuvenation, security, safety, and power management. In addition, the book: <ul> <li>Explains real-time embedded software modeling and design with finite state machines, Petri nets, and UML; and real-time constraints verification with the model checking tool NuSMV</li> <li>Features real-world examples in finite state machines, model checking, real-time system design with UML, and more</li> <li>Covers embedded computer programing, designing for reliability, and designing for safety</li> <li>Explains how to make engineering trade-offs of power use and performance</li> <li>Investigates practical issues concerning software reliability, aging, rejuvenation, security, and power management</li> </ul> <br> <p><em>Real-Time Embedded Systems</em> is a valuable resource for those responsible for real-time and embedded software design, development, and management. It is also an excellent textbook for graduate courses in computer engineering, computer science, information technology, and software engineering on embedded and real-time software systems, and for undergraduate computer and software engineering courses.

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