Table of Contents

Cover

Title Page

Dedication

About the Author

Preface

Acknowledgments

Chapter 1: Introduction

1.1 Testing for ESD, EMI, EOS, EMC, and Latchup
1.2 Component and System Level Testing
1.3 Qualification Testing
1.4 ESD Standards
1.5 Component Level Standards
1.6 System Level Standards
1.7 Factory and Material Standards
1.8 Characterization Testing
1.9 ESD Library Characterization and Qualification
1.10 ESD Component Standards and Chip Architectures
1.11 System Level Characterization
1.12 Summary and Closing Comments
Problems
References

Chapter 2: Human Body Model

2.1 History
2.2 Scope
2.3 Purpose
2.4 Pulse Waveform
2.5 Equivalent Circuit
2.6 Test Equipment
2.7 Test Sequence and Procedure
2.8 Failure Mechanisms
2.9 HBM ESD Current Paths
2.10 HBM ESD Protection Circuit Solutions
2.11 Alternate Test Methods
2.12 HBM Two-Pin Stress
2.13 HBM Small Step Stress
2.14 Summary and Closing Comments
Problems
References

Chapter 3: Machine Model

3.1 History
3.2 Scope
3.3 Purpose
3.4 Pulse Waveform
3.5 Equivalent Circuit
3.6 Test Equipment
3.7 Test Sequence and Procedure
3.8 Failure Mechanisms
3.9 MM ESD Current Paths
3.10 MM ESD Protection Circuit Solutions
3.11 Alternate Test Methods
3.12 Machine Model to Human Body Model Ratio
3.13 Machine Model Status as an ESD Standard
3.14 Summary and Closing Comments
Problems
References

Chapter 4: Charged Device Model (CDM)

4.1 History
4.2 Scope
4.3 Purpose
4.4 Pulse Waveform
4.5 Equivalent Circuit
4.6 Test Equipment
4.7 Test Sequence and Procedure
4.8 Failure Mechanisms
4.9 CDM ESD Current Paths
4.10 CDM ESD Protection Circuit Solutions
4.11 Alternative Test Methods
4.12 Charged Board Model (CBM)
4.13 Summary and Closing Comments
Problems
References

Chapter 5: Transmission Line Pulse (TLP) Testing

5.1 History
5.2 Scope
5.3 Purpose
5.4 Pulse Waveform
5.5 Equivalent Circuit
5.6 Test Equipment
5.7 Test Sequence and Procedure
5.8 TLP Pulsed I–V Characteristic
5.9 Alternate Methods
5.10 TLP-to-HBM Ratio
5.11 Summary and Closing Comments
Problems
References

Chapter 6: Very Fast Transmission Line Pulse (VF-TLP) Testing

6.1 History
6.2 Scope
6.3 Purpose
6.4 Pulse Waveform
6.5 Equivalent Circuit
6.6 Test Equipment Configuration
6.7 Test Sequence and Procedure
6.8 VF-TLP Pulsed I–V Characteristics
6.9 Alternate Test Methods
6.10 Summary and Closing Comments
Problems
References

Chapter 7: IEC 61000-4-2

7.1 History
7.2 Scope
7.3 Purpose
7.4 Pulse Waveform
7.5 Equivalent Circuit
7.6 Test Equipment
7.7 Test Sequence and Procedure
7.8 Failure Mechanisms
7.9 IEC 61000-4-2 ESD Current Paths
7.10 ESD Protection Circuitry Solutions
7.11 Alternative Test Methods
7.12 Summary and Closing Comments
Problems
References

Chapter 8: Human Metal Model (HMM)

8.1 History
8.2 Scope
8.3 Purpose
8.4 Pulse Waveform
8.5 Equivalent Circuit
8.6 Test Equipment
8.7 Test Configuration
8.8 Test Sequence and Procedure
8.9 Failure Mechanisms
8.10 ESD Current Paths
8.11 ESD Protection Circuit Solutions
8.12 Summary and Closing Comments
Problems
References

Chapter 9: IEC 61000-4-5

9.1 History
9.2 Scope
9.3 Purpose
9.4 Pulse Waveform
9.5 Equivalent Circuit
9.6 Test Equipment
9.7 Test Sequence and Procedure
9.8 Failure Mechanisms
9.9 IEC 61000-4-5 ESD Current Paths
9.10 ESD Protection Circuit Solutions
9.11 Alternate Test Methods
9.12 Summary and Closing Comments
Problems
References

Chapter 10: Cable Discharge Event (CDE)

10.1 History
10.2 Scope
10.3 Purpose
10.4 Cable Discharge Event – Charging, Discharging, and Pulse Waveform
10.5 Equivalent Circuit
10.6 Test Equipment
10.7 Test Measurement
10.8 Test Procedure
10.9 Measurement of a Cable in Different Conditions
10.10 Transient Field Measurements
10.11 Telecommunication Cable Discharge Test System
10.12 Cable Discharge Current Paths
10.13 Failure Mechanisms
10.14 Cable Discharge Event (CDE) Protection
10.15 Alternative Test Methods
10.16 Summary and Closing Comments
Problems
References

Chapter 11: Latchup

11.1 History
11.2 Purpose
11.3 Scope
11.4 Pulse Waveform
11.5 Equivalent Circuit
11.6 Test Equipment
11.7 Test Sequence and Procedure
11.8 Failure Mechanisms
11.9 Latchup Current Paths
11.10 Latchup Protection Solutions
11.11 Alternate Test Methods
11.12 Single Event Latchup (SEL) Test Methods
11.13 Summary and Closing Comments
Problems
References

Chapter 12: Electrical Overstress (EOS)

12.1 History
12.2 Scope
12.3 Purpose
12.4 Pulse Waveform
12.5 Equivalent Circuit
12.6 Test Equipment
12.7 Test Procedure and Sequence
12.8 Failure Mechanisms
12.9 Electrical Overstress (EOS) Protection Circuit Solutions
12.10 Electrical Overstress (EOS) Testing – TLP Method and EOS
12.11 Electrical Overstress (EOS) Testing – DC and Transient Latchup Testing
12.12 Summary and Closing Comments
Problems
References

Chapter 13: Electromagnetic Compatibility (EMC)

13.1 History
13.2 Purpose
13.3 Scope
13.4 Pulse Waveform
13.5 Equivalent Circuit
13.6 Test Equipment
13.7 Test Procedures
13.8 Failure Mechanisms
13.9 ESD/EMC Current Paths
13.10 EMC Solutions
13.11 Alternative Test Methods
13.12 EMC/ESD Product Evaluation – IC Prequalification
13.13 EMC/ESD Scanning Detection – Upset Evaluation
13.14 EMC/ESD Product Qualification Process
13.15 Alternative ESD/EMC Scanning Methods
13.16 Current Reconstruction Methodology
13.17 Printed Circuit Board (PCB) Design EMC Solutions
13.18 Summary and Closing Comments
Problems
References

Appendix A: Glossary of Terms

Appendix A: Standards

B.1 ESD Association
B.2 International Organization of Standards
B.3 IEC
B.4 RTCA
B.5 Department of Defense
B.6 Military Standards
B.7 Airborne Standards and Lightning

Index

End User License Agreement

List of Illustrations

Chapter 1: Introduction

Figure 1.1 ESD, EMI, EOS, and EMC
Figure 1.2 Component tests
Figure 1.3 System level tests
Figure 1.4 Qualification testing
Figure 1.5 Repeatability and Reproducibility
Figure 1.6 SP to STM Process
Figure 1.7 Mandel k-statistics plot
Figure 1.8 Mandel h-statistics plot
Figure 1.9 Factory and material standards
Figure 1.10 Semiconductor chip level characterization
Figure 1.11 Failure mechanisms, standards, and chip architecture
Figure 1.12 System level characterization

Chapter 2: Human Body Model

Figure 2.1 Human body model (HBM) pulse waveform
Figure 2.2 Human body model (HBM) equivalent circuit model
Figure 2.3 Human body model (HBM) equivalent circuit model with parasitics
Figure 2.4 Human body model (HBM) source
Figure 2.5 (a) Human body model (HBM) commercial test system – Hanwa S5000R. (b) Human body model (HBM) commercial test system – Hanwa HED-N5000
Figure 2.6 Human body model (HBM) wafer level commercial test system
Figure 2.7 Human body model (HBM) test sequence
Figure 2.8 Human body model (HBM) incremental step stress test sequence
Figure 2.9 Human body model (HBM) failure mechanism – diode failure
Figure 2.10 Human body model (HBM) failure mechanism – MOSFET failure
Figure 2.11 Human body model (HBM) failure mechanism – series cascode MOSFET failure
Figure 2.12 Human body model (HBM) ESD event current paths – signal pin to power (V_DD)
Figure 2.13 HBM ESD event current paths – signal pin to ground (V_SS)
Figure 2.14 HBM ESD event current paths – power rail (V_DD) to power (V_SS)
Figure 2.15 HBM ESD event current paths – signal pin to signal pin within a common power domain
Figure 2.16 HBM ESD event current paths – signal pin to alternate ground rail domain to domain
Figure 2.17 HBM signal pin ESD protection circuits – dual diode
Figure 2.18 HBM signal pin ESD protection circuit – grounded gate NMOS (GGNMOS)
Figure 2.19 HBM ESD protection circuits – silicon controlled rectifier
Figure 2.20 HBM ESD protection device – power rail to power rail protection
Figure 2.21 Human body model (HBM) ESD protection circuits – ground-to-ground network
Figure 2.22 Alternate test methods
Figure 2.23 HBM split fixture testing
Figure 2.24 HBM sample testing
Figure 2.25 Human body model (HBM) wafer level test equipment
Figure 2.26 Human body model Two-Pin test system (Reproduced with permission of the Hanwa Corporation)
Figure 2.27 HBM two-pin stress test equipment – Grund Technical Solutions Arcus HBM wafer and device test system

Chapter 3: Machine Model

Figure 3.1 MM pulse waveform
Figure 3.2 MM and HBM waveform comparison
Figure 3.3 MM equivalent circuit model
Figure 3.4 MM equivalent circuit model with parasitics
Figure 3.5 MM source
Figure 3.6 (a) MM commercial test system. (b) MM commercial test system – MK1 Thermo-KeyTek (Reproduced with permission of Thermo Fisher Scientific)
Figure 3.7 MM test sequence
Figure 3.8 MM incremental step stress test sequence
Figure 3.9 MM ESD failure mechanisms
Figure 3.10 MM ESD event current paths – signal pin to power (V_DD)
Figure 3.11 MM ESD event current paths – signal pin to ground power (V_SS)
Figure 3.12 MM ESD event – power rail (V_DD) to ground power rail (V_SS)
Figure 3.13 MM ESD event – power ground (V_SS) to ground power rail (V_SS)
Figure 3.14 MM ESD protection circuits – dual diode
Figure 3.15 MM ESD protection circuits – grounded gate NMOS (GGNMOS)
Figure 3.16 MM ESD protection circuits – bidirectional silicon controlled rectifier (SCR)
Figure 3.17 MM ESD protection circuits – V_DD to V_SS power rail RC-triggered power clamp network and return diode
Figure 3.18 MM ESD protection circuits – V_SS-to-V_SS rail-to-rail network
Figure 3.19 Small charge model (SCM) equivalent circuit (Reproduced with permission of Hanwa Corporation)
Figure 3.20 Small charge model (SCM) source (Reproduced with permission of Hanwa Corporation)
Figure 3.21 Small charge model (SCM) commercial tester
Figure 3.22 HBM to MM ratio
Figure 3.23 HBM to MM ratio versus HBM voltage

Chapter 4: Charged Device Model (CDM)

Figure 4.1 Charged device models – CDM, SDM, and CBM
Figure 4.2 Charged device model pulse waveform
Figure 4.3 Charged device model (CDM) and HBM waveform comparison
Figure 4.4 (a) Charged Device Model equivalent circuit. (b) Charged Device Model equivalent circuit with parasitics associated with the chassis
Figure 4.5 Charged device model tester
Figure 4.6 (a) Charged device model (CDM) commercial test system Hanwa HED-C5000. (b) Charged device model (CDM) commercial test system Hanwa HED-C5000R (Reproduced with permission of the Hanwa Corporation)
Figure 4.7 Charged device model (CDM) commercial test system – Thermo KeyTek Orion2
Figure 4.8 Charged device model (CDM) test sequence
Figure 4.9 Charged device model (CDM)-induced failure mechanism – receiver gate failure
Figure 4.10 Charged device model (CDM)-induced failure mechanism – interconnects
Figure 4.11 Charged device model (CDM) ESD event current path – charged V_SS positive polarity and grounded receiver pin
Figure 4.12 CDM ESD current paths – charged V_DD positive polarity and grounded receiver pin
Figure 4.13 Charged device model (CDM) ESD protection circuits – dual-diode–resistor–dual-diode network
Figure 4.14 Charged device model (CDM) ESD protection circuits – dual-diode–resistor–grounded gate NMOS
Figure 4.15 Charged device model (CDM) failure mechanisms in silicon-on-insulator (SOI) technology
Figure 4.16 Charged board model
Figure 4.17 FICDM and field-induced charged board model (FICBM) waveform comparison
Figure 4.18 Equivalent circuit schematic with FICDM and FICBM capacitive elements
Figure 4.19 Field-induced charged board model (FICBM) testing of populated printed circuit board
Figure 4.20 (a) CBM failure of an ESD diode. (b) CBM failure of an ESD diode. (c) CBM failure of interconnects

Chapter 5: Transmission Line Pulse (TLP) Testing

Figure 5.1 Pulse testing
Figure 5.2 Transmission line pulse (TLP) waveform
Figure 5.3 Transmission line pulse waveform (expansion)
Figure 5.4 Transmission line pulse (TLP) equivalent circuit
Figure 5.5 Transmission line pulse (TLP) current source configuration
Figure 5.8 Transmission line pulse (TLP) time domain reflection transmission (TDRT) configuration
Figure 5.6 Transmission line pulse (TLP) time domain reflectometry (TDR) configuration
Figure 5.7 Transmission line pulse (TLP) time domain transmission (TDT) configuration
Figure 5.9 (a) Transmission line pulse (TLP) commercial test equipment – Barth system
Figure 5.10 Transmission line pulse (TLP) commercial test equipment – Thermo KeyTek Bench Top Celestron™ Flexible Bench Top TLP/VF-TLP System
Figure 5.11 TLP test procedure and sequence
Figure 5.12 TLP measurement window and the current overshoot
Figure 5.13 TLP analysis – TDR voltage waveform
Figure 5.14 TLP analysis – TDR current waveform
Figure 5.15 TLP analysis – TDR results for current and voltage
Figure 5.16 Construction of transmission line pulse (TLP) I–V characteristic
Figure 5.17 Power versus time plot
Figure 5.18 Test sequence for Wunsch–Bell curve construction
Figure 5.19 Wunsch–Bell curves: power-to-failure versus pulse width
Figure 5.20 Long-pulse TLP waveform
Figure 5.21 Wunsch–Bell curve highlighting long duration TLP time domain
Figure 5.22 Transmission line pulse (TLP) and HBM pulse waveform comparison

Chapter 6: Very Fast Transmission Line Pulse (VF-TLP) Testing

Figure 6.1 Very fast TLP testing overview
Figure 6.2 Very fast transmission line pulse (VF-TLP) pulse waveform
Figure 6.3 Very fast transmission line pulse (VF-TLP) and TLP waveform comparison
Figure 6.4 Very fast transmission line pulse (VF-TLP) equivalent circuit
Figure 6.5 Very fast transmission line pulse (VF-TLP) TDR configuration
Figure 6.6 Very fast transmission line pulse (VF-TLP) time domain transmission (TDT) configuration
Figure 6.7 Very fast transmission line pulse (VF-TLP) time domain transmission (TDRT) configuration
Figure 6.8 (a) Very fast transmission line pulse (VF-TLP) test system with matching network. (b) Very fast transmission line pulse (VF-TLP) test system (Whalen and Domingos)
Figure 6.9 (a) Very fast transmission line pulse (VF-TLP) commercial test equipment – Barth Model 4012 VF-TLP+™
Figure 6.10 VF-TLP test sequence
Figure 6.11 VF-TLP measurement window
Figure 6.12 VF-TLP analysis – TDR voltage waveform
Figure 6.13 VF-TLP analysis – TDR current waveform
Figure 6.14 Very fast transmission line pulse (TLP) I–V characteristic analysis construction
Figure 6.15 Very fast transmission line pulse (TLP) I–V characteristic analysis construction
Figure 6.16 Power versus time plot
Figure 6.17 Wunsch–Bell curves: power-to-failure versus pulse width
Figure 6.18 Wunsch–Bell curve with VF-TLP and TLP result
Figure 6.19 (a) Very fast transmission line pulse (VF-TLP) test system. (b) Very fast transmission line pulse (VF-TLP) test system for RF parameter analysis with matching network
Figure 6.20 Ultrafast transmission line pulse (UF-TLP) test system
Figure 6.21 Ultrafast transmission line pulse (UF-TLP) pulse waveform
Figure 6.22 Ultrafast transmission line pulse (UF-TLP) results for a tunneling magnetoresistor (TMR) structure

Chapter 7: IEC 61000-4-2

Figure 7.1 IEC 61000-4-2
Figure 7.2 IEC 61000-4-2 pulse waveform
Figure 7.3 IEC 61000-4-2 ESD gun equivalent circuit (Reproduced with permission of Thermo Fisher Scientific)
Figure 7.4 (a) IEC 61000-4-2 commercial test equipment – ESD gun. (b) IEC 61000-4-2 MiniZap ESD simulator – Thermo KeyTek
Figure 7.5 IEC 61000-4-2 test equipment – table configuration
Figure 7.6 IEC 61000-4-2 versus HBM waveform comparison
Figure 7.7 IEC 61000-4-2 test procedure
Figure 7.8 IEC 61000-4-2 induced failure mechanism
Figure 7.9 IEC 61000-4-2 ESD event current paths – V_SS positive polarity
Figure 7.10 IEC 61000-4-2 ESD event current paths
Figure 7.11 IEC 61000-4-2 ESD protection power clamp
Figure 7.12 IEC 61000-4-2 ESD protection circuits
Figure 7.13 IEC 61000-4-2 ESD event – power grid definition

Chapter 8: Human Metal Model (HMM)

Figure 8.1 Human metal model (HMM) testing overview
Figure 8.2 Human metal model (HMM) pulse waveform
Figure 8.3 Human metal model (HMM) ESD gun equivalent circuit
Figure 8.4 Commercial HMM test system – Barth 4702 HMM+™
Figure 8.5 (a) Human metal model (HMM) – horizontal test configuration. (b) Human metal model (HMM) test equipment – vertical table test configuration
Figure 8.6 Schematic layout of IEC 50 Ω coaxial source test fixture board
Figure 8.7 Layout of IEC 50 Ω coaxial source test fixture board showing ground connections
Figure 8.8 (a) HMM with powered board. (b) Human metal model (HMM) source test fixture board (Reproduced with permission from Grund Technical Solutions)
Figure 8.9 Human metal model (HMM) test sequence
Figure 8.10 Human metal model (HMM) current waveform verification – physical arrangements
Figure 8.11 Simultaneous measurement of current probe IEC and the Fischer Custom Communication current probe F-65A
Figure 8.12 Human metal model (HMM) current probe waveform comparison
Figure 8.13 HMM ESD event current paths – V_SS positive polarity
Figure 8.14 Human metal model (HMM) ESD protection solution – dedicated V_DD and V_SS power bus
Figure 8.15 Human metal model (HMM) ESD event – power grid definition

Chapter 9: IEC 61000-4-5

Figure 9.1 IEC 61000-4-5
Figure 9.2 IEC 61000-4-5 surge test pulse open-circuit waveform
Figure 9.3 IEC 61000-4-5 surge test pulse short-circuit waveform
Figure 9.4 IEC 61000-4-5 equivalent circuit of a transient surge generator
Figure 9.5 (a) IEC 61000-4-5 high voltage transient surge commercial test equipment. (b) IEC 61000-4-5 high voltage transient surge commercial test equipment – EMCPro Plus^TM EMC Test System
Figure 9.6 IEC 61000-4-5 test procedure
Figure 9.7 IEC 61000-4-5 ESD protection circuit I–V characteristics
Figure 9.8 IEC 61000-4-5 ESD protection circuit for ground connections

Chapter 10: Cable Discharge Event (CDE)

Figure 10.1 Cable discharge event (CDE)
Figure 10.2 (a) Charging process on Category 5 (CAT 5) cable. (b) Cable discharge event (CDE) discharging process and example test setup. (c) Cable discharge event (CDE) model pulse waveform
Figure 10.3 (a) Cable discharge event (CDE) equivalent circuit model as a lossless transmission line. (b) Cable discharge event (CDE) equivalent circuit with parasitics as a lossy transmission line
Figure 10.4 Cable discharge event (CDE) commercial test system – ESDEMC ES631 – LAN cable discharge event (CDE) evaluation system
Figure 10.5 (a) Test equipment. (b) Test equipment target and adapter
Figure 10.6 Cable discharge event (CDE) measurement – high-impedance test generator
Figure 10.7 Cable discharge event (CDE) measurement – low-impedance test generator
Figure 10.8 (a) Low-impedance transmission line waveform. (b) Capturing system response to reference waveform. (c) Capturing system response – alternate current transducer. (d) Capturing system response – alternate current transducer
Figure 10.9 (a) Constant impedance tapered transmission line. (b) Constant impedance tapered transmission line. (c) Tapered transmission line (Reproduced with permission from Barth Electronics Corp.)
Figure 10.10 (a) ESD current sensor. (b) ESD current sensor. (c) ESD current sensor (Reproduced with permission from ESD Association)
Figure 10.11 (a) Cable discharge event (CDE) measurement – test procedure. (b) Cable discharge test configuration (Reproduced with permission from ESD Association)
Figure 10.12 Cable discharge event (CDE) measurement – holding cable (Reproduced with permission from ESD Association)
Figure 10.13 (a) Cable discharge event (CDE) measurement – taped to vertical wall. (b) Cable discharge event (CDE) measurement – taped to vertical wall versus floating cable (Reproduced with permission from ESD Association)
Figure 10.14 (a) Cable discharge event (CDE) measurement – pulse analysis summary. (b) Cable discharge event (CDE) measurement – pulse analysis summary – initial peak current. (c) Cable discharge event (CDE) measurement – pulse analysis summary – plateau current (Reproduced with permission from ESD Association)
Figure 10.15 (a) Transient discharge – discharge current. (b) Transient discharge – magnetic field. (c) Magnetic current loop. (d) Transient discharge – electric field. (e) Monopole antenna loops (Reproduced with permission from ESD Association)
Figure 10.26 Antenna-induced voltage (Reproduced with permission from ESD Association)
Figure 10.17 Telecommunication CDE test system
Figure 10.18 Telecommunication CDE test system
Figure 10.19 Cable discharge-induced latchup
Figure 10.20 Cable discharge event (CDE) system level solutions
Figure 10.21 Cable discharge event (CDE) validation test system

Chapter 11: Latchup

Figure 11.1 Latchup testing evolution
Figure 11.2 Latchup cross section
Figure 11.3 (a) Latchup two transistor representation. (b) Latchup four-stripe PNPN test structure
Figure 11.4 Latchup current–voltage (I–V) characteristic
Figure 11.5 Latchup waveform for DC latchup
Figure 11.6 Transient latchup waveform
Figure 11.7 Latchup equivalent circuit model
Figure 11.8 Example wafer level latchup test system
Figure 11.9 Thermo Scientific MK4™ commercial latchup test system
Figure 11.10 (a) Latchup test procedure and test flow. (b) Latchup test procedure – positive I-test. (c) Latchup test procedure – negative I-test
Figure 11.11 (a) Latchup failure mechanism – chip level damage. (b) Latchup failure mechanism – package level damage
Figure 11.12 (a) Internal latchup current paths. (b) External latchup current paths
Figure 11.13 Classes of latchup protection solutions
Figure 11.14 Latchup design layout solutions – internal
Figure 11.15 Latchup design layout solutions – external
Figure 11.16 Latchup circuit design solutions
Figure 11.17 Latchup system level design solutions
Figure 11.18 PICA – TLP test method
Figure 11.19 (a) Photon emissions overlaid on semiconductor chip design. (b) Photon emissions from ESD diode. (c) Photon emission count versus time
Figure 11.20 Photon emission test system
Figure 11.21 (a) Photon emission image. (b) Photon emission image (expanded)
Figure 11.22 Single event latchup (SEL)
Figure 11.23 Testing technique

Chapter 12: Electrical Overstress (EOS)

Figure 12.1 Field failure categories
Figure 12.2 EOS versus ESD waveforms
Figure 12.4 EOS and ESD event time constant hierarchy
Figure 12.5 Test procedure
Figure 12.6 EOS failure mechanisms
Figure 12.7 EOS failure mechanism – wire bond
Figure 12.8 EOS failure mechanism – packaging
Figure 12.9 EOS failure mechanism – bond pads
Figure 12.10 (a) Electrical overvoltage (EOV) protection classification. (b) Electrical overvoltage (EOV) protection network
Figure 12.11 Electrical overcurrent (EOC) protection
Figure 12.12 (a) EOS protection – Schottky diode. (b) EOS protection – Zener diode. (c) EOS protection – operational amplifier with Schottky and Zener protection
Figure 12.13 (a) EOS protection – metal oxide varistor (MOV). (b) EOS protection – metal oxide varistor (MOV) for power supply
Figure 12.14 (a) EOS protection – gas discharge tube (GDT). (b) EOS protection – gas discharge tube (GDT) I–t plot
Figure 12.15 EOS protection – thermal circuit breakers
Figure 12.16 EOS protection – soft start EOC and EOV protection circuitry
Figure 12.17 Wunsch–Bell power to failure plot
Figure 12.18 Slow and fast EOS domain in the Wunsch–Bell curve

Chapter 13: Electromagnetic Compatibility (EMC)

Figure 13.1 Electromagnetic compatibility issues
Figure 13.2 Electromagnetic compatibility pulse waveforms
Figure 13.3 Commercial EMC test system – EMCPro Plus™ EMC (Reproduced by permission of Thermo Scientific Fisher)
Figure 13.4 (a) EMC/ESD high-level diagram
Figure 13.5 EMC/ESD scanning system – large system
Figure 13.6 ESD/EMC scanning test procedure
Figure 13.7 EMC current paths – the return current
Figure 13.8 Scanning methodologies
Figure 13.9 Susceptibility and vulnerability
Figure 13.10 ESD/EMC scanning stimulus
Figure 13.11 ESD/EMC qualification process
Figure 13.12 ESD/EMC comparison of reproducibility
Figure 13.13 (a) ESD/EMC failure threshold mapping
Figure 13.14 (a) ESD immunity IC level. (b) ESD immunity IC pin response. (c) ESD immunity IC pin failure levels. (d) ESD/EMC image comparison (vendors A and B)
Figure 13.15 ESD immunity at ATE stage
Figure 13.16 Motherboard image scan
Figure 13.17 EOS and residual current
Figure 13.18 Printed circuit board trace electromagnetic emissions
Figure 13.19 Current reconstruction – test procedure and sequence
Figure 13.20 Printed circuit board emissions
Figure 13.21 Printed circuit board emissions
Figure 13.22 Printed circuit board design

ESD Series

ESD: Circuits and Devices, 2nd Edition

June 2015

ESD: Analog Circuits and Design

October 2014

Electrical Overstress (EOS): Devices, Circuits and Systems

October 2013

ESD Basics: From Semiconductor Manufacturing to Product Use

September 2012

ESD: Design and Synthesis

March 2011

ESD: Failure Mechanisms and Models

July 2009

Latchup

December 2007

ESD: RF Technology and Circuits

September 2006

ESD: Circuits and Devices

November 2005

ESD Physics and Devices

September 2004

John Wiley & Sons Ltd, The Atrium, Southern Gate, Chichester, West Sussex, PO19 8SQ, United Kingdom

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Description: Chichester, UK ; Hoboken, NJ : John Wiley & Sons, 2016. | Series: ESD series | Includes bibliographical references and index.

Identifiers: LCCN 2016023736 (print) | LCCN 2016033086 (ebook) | ISBN 9780470511916 (cloth) | ISBN 9781118707142 (pdf) | ISBN 9781118707159 (epub)

Subjects: LCSH: Electronic circuits-Effect of radiation on. | Electronic apparatus and appliances-Testing. | Electric discharges--Detection. | Electric discharges-Measurement. | Electrostatics.

Classification: LCC TK7870.285 .V65 2016 (print) | LCC TK7870.285 (ebook) | DDC 621.3815/4-dc23

About the Author

Dr Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for “Contributions in ESD protection in CMOS, Silicon on Insulator and Silicon Germanium Technology.” He received his BS in Engineering Science from the University of Buffalo (1979); a first MS EE (1981) from Massachusetts Institute of Technology (MIT); a second degree EE Degree (Engineer Degree) from MIT; an MS Engineering Physics (1986); and a PhD in electrical engineering (EE) (1991) from University of Vermont under IBM's Resident Study Fellow program.

Voldman was a member of the semiconductor development of IBM for 25 years. He was a member of the IBM's Bipolar SRAM, CMOS DRAM, CMOS logic, Silicon on Insulator (SOI), 3D memory team, BiCMOS and Silicon Germanium, RF CMOS, RF SOI, smart power technology development, and image processing technology teams. In 2007, Voldman joined the Qimonda Corporation as a member of the DRAM development team, working on 70, 58, 48, and 32 nm CMOS DRAM technology. In 2008, Voldman worked as a full-time ESD consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) supporting ESD and latchup development for 45 nm CMOS technology and a member of the TSMC Standard Cell Development team in Hsinchu, Taiwan. In 2009–2011, Steve became a Senior Principal Engineer working for the Intersil Corporation working on analog, power, and RF applications in RF CMOS, RF Silicon Germanium, and SOI. In 2013–2014, Dr Voldman was a consultant for the Samsung Electronics Corporation in Dongtan, South Korea.

Dr Voldman was chairman of the SEMATECH ESD Working Group from 1995 to 2000. In his SEMATECH Working Group, the effort focused on ESD technology benchmarking, the first transmission line pulse (TLP) standard development team, strategic planning, and JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. Steven Voldman has been a member of the ESD Association Board of Directors and Education Committee. He initiated the “ESD on Campus” program that was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Senegal, Malaysia, Philippines, Thailand, India, and China. Dr Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.

He is a recipient of 258 issued US patents and has written over 150 technical papers in the area of ESD and CMOS latchup. Since 2007, he has served as an expert witness in patent litigation and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing, and patent litigation. In his LLC, Voldman served as an expert witness for cases on DRAM development, semiconductor development, integrated circuits, and ESD. He is presently writing patents for law firms. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents in Malaysia, Sri Lanka, and the United States.

Dr Voldman also has written an article for Scientific American and is an author of the first book series on ESD, latchup, and EOS (nine books): ESD: Physics and Devices; ESD: Circuits and Devices; ESD: RF Technology and Circuits; Latchup; ESD: Failure Mechanisms and Models; ESD: Design and Synthesis; ESD Basics: From Semiconductor Manufacturing to Product Use; Electrical Overstress (EOS): Devices, Circuits and Systems; and ESD: Analog Circuits and Design, as well as a contributor to the book Silicon Germanium: Technology, Modeling, and Design and a chapter contributor to Nanoelectronics: Nanowires, Molecular Electronics, and Nanodevices. In addition, the International Chinese editions of book ESD: Circuits and Devices; ESD: RF Technology and Circuits; ESD: Design and Synthesis; and ESD Basics: From Semiconductor Manufacturing to Product Use are also released.

Preface

The book ESD Testing: From Components to Systems was targeted for the semiconductor process and device engineer, the circuit designer, the ESD/latchup test engineer, and the ESD engineer. In this book, a balance is established between the technology and testing.

The first goal of this book is to teach the ESD models used today. There are many ESD test models, and more types are being developed today and in the future.

The second goal is to show recent test systems and test standards. Significant change in both the test methodologies and issues are leading to proposal of new ESD models, introduction of new standards, and an impact on product diversity and product variety.

The third goal is to expose the reader to the growing number of new testing methodologies, concepts, and equipment. In this book, commercial test equipment is shown as an example to demonstrate the “state-of-the-art” of ESD testing. Significant progress has been made in recent years in ESD, EOS, and EMC.

The fourth goal, as previously done in the ESD book series, is to teach testing as an ESD design practice. ESD testing can be used as a design methodology or an ESD tool. ESD testing can lead to understanding of the fundamental practices of ESD design and the ESD design discipline. This practice uses ESD testing for “de-bugging” and diagnosis.

The fifth goal is to provide a book that can view the different test methods independently. Each chapter is independent so that the reader can study or read about a test model independent of the other test models.

The sixth goal is to provide a text where one can compare the interrelationship between one ESD model and another ESD model. In many cases, there is commonality between the test waveform, the test procedure, and even failure mechanisms.

The seventh goal is to provide a text structure similar to a standard or standard test method, but read easier than reading a standard document. The goal was also to reduce the level of details of the standard to simplify the understanding.

The book ESD Testing: From Components to Systems consists of the following:

Chapter 1 introduces the reader to fundamentals and concepts of the electrostatic discharge (ESD) models and issues.
Chapter 2 discusses the human body model (HBM). It discusses the purpose, scope, waveforms, test procedures, and test systems. In this chapter, both the wafer-level and product-level test methodologies are discussed. This chapter includes HBM failure mechanisms to circuit solutions. Alternative test methodologies such as sampling and split fixture methods are reviewed.
Chapter 3 discusses the machine model (MM). It discusses the purpose, scope, waveforms, test procedures, and test systems. In this chapter, both the wafer-level and product-level test methodologies are discussed. This chapter includes MM failure mechanisms to circuit solutions. Alternative test methodologies such as the small charge model (SCM) are discussed. In addition, correlation relations of HBM to MM ratio are analyzed and reviewed.
Chapter 4 discusses the charged device model (CDM). It discusses the purpose, scope, waveforms, CDM test procedures, and CDM test systems. This chapter includes CDM failure mechanisms to circuit solutions to avoid CDM failures. Alternative test methodologies such as the socketed device model (SDM) and charged board model (CBM) are discussed.
Chapter 5 discusses the transmission line pulse (TLP) methodology and its importance in the semiconductor industry and ESD development. It discusses the purpose, scope, waveforms, TLP pulsed I–V characteristics, TLP test procedures, and TLP test system configurations. TLP current source, time domain reflection (TDR), time domain transmission (TDT), and time domain reflection and transmission (TDRT) configurations is explained
Chapter 6 discusses the very fast transmission line pulse (VF-TLP) methodology. It discusses the purpose, scope, waveforms, VF-TLP pulsed I–V characteristics, VF-TLP test procedures, and VF-TLP test system configurations. Alternative test methods such as ultra fast transmission line pulse (UF-TLP) are discussed.
Chapter 7 discusses the system-level method, known as IEC 61000-4-2. It discusses the purpose, scope, IEC 61000-4-2 waveforms, IEC 61000-4-2 table configurations, and requirements. Failure mechanisms and circuit solutions to avoid failures are explained.
Chapter 8 discusses the human metal model (HMM) method. The HMM model has many similarities to the system-level method, known as IEC 61000-4-2. It discusses the purpose, scope, waveforms, HMM table configurations, and requirements as well as the distinctions and commonality to the IEC 61000-4-2 test method.
Chapter 9 discusses the system-level transient surge method, known as IEC 61000-4-5. It discusses the purpose, scope, IEC 61000-4-5 waveforms, IEC 61000-4-5 table configurations, and requirements. Failure mechanisms and circuit solutions to avoid failures are explained. The distinction from the IEC 61000-4-2 is highlighted.
Chapter 10 discusses the cable discharge event (CDE) method. It discusses the purpose, scope, waveforms, cable configurations, and impact on the pulse event. Examples of cable-induced failures are given, as well as circuit- and system-level solutions to avoid chip and system failures.
Chapter 11 discusses latchup. It addresses latchup testing, characterization, and design. It also addresses latchup test techniques for product-level testing. Technology benchmarking to ground rule development is also briefly discussed.
Chapter 12 discusses electrical overstress (EOS). It focuses on electrical and thermal safe operating area (SOA) and how EOS occurs. It also focuses on how to distinguish latchup from EOS events.
Chapter 13 discusses electromagnetic compatibility (EMC). It addresses ESD and EMC testing and characterization methods. It also serves as a brief introduction to this large subject matter.

Hopefully, the book covers the trends and directions of ESD testing discipline.

Enjoy the text, and enjoy the subject of ESD testing.

B”H
Steven H. Voldman
IEEE Fellow

Acknowledgments

I would like to thank the individuals who have helped me learn about experimental work, high current testing, high voltage testing, electrostatic discharge (ESD) testing, electrical overstress (EOS), and standards development. In the area of ESD, EOS, and latchup testing, I would like to thank for all the support received from SEMATECH, the ESD Association, and the JEDEC organizations.

I would like to thank the SEMATECH organization for allowing me to establish the SEMATECH ESD Work Group: this work group initiated the ESD technology benchmarking test structures, the JEDEC-ESD Association collaboration on ESD standard development, alternate test methods, and most important, the initiation of the transmission line pulse (TLP) standard development.

I thank the ESD Association ESD Work Group (WG) standard committees for many years of discussion on standard developments and on human body model (HBM), machine model (MM), charged device model (CDM), cable discharge event (CDE), human metal model (HMM), TLP testing, and very fast transmission line pulse (VF-TLP) testing. I also thank the ESD Association Standards Development Work Group 5.5 TLP testing committee. We were very fortunate to have a highly talented and motivated team to rapidly initiate the TLP and VF-TLP documents for the semiconductor industry; this included for the development of the TLP and VF-TLP standards, which was a significant accomplishment that has influenced the direction of ESD testing. I am thankful to my colleagues Robert Ashton, Jon Barth, David Bennett, Mike Chaine, Horst Gieser, Evan Grund, Leo G. Henry, Mike Hopkins, Hugh Hyatt, Mark Kelly, Tom Meuse, Doug Miller, Scott Ward, Kathy Muhonen, Nathaniel Peachey, Jeff Dunihoo, Keichi Hasegawa, Jin Min, Yoon Huh, and Wei Huang. I am also thankful to Tze Wee Chen of Stanford University for discussions on the ultra-fast transmission line pulse (UF-TLP) testing.

I am grateful to the Oryx Instrument ESD test development team for years of ESD test support and the Thermo Fisher Scientific team of David Bennett, Mike Hopkins, Tom Meuse, Tricia Rakey, and Kim Baltier. My sincere thanks goes to Jon Barth of Barth Electronics for usage of the images of the Barth test equipment for this text; Keichi Hasegawa of Hanwa Electronics for the images of the Hanwa test equipment; Yoon Huh and Jin Min of Amber Precision Instruments for the scanning images and the test equipment; Wei Huang for the images of the ESDEMC test equipment; Jeff Dunnihoo of Pragma Design Inc for the current reconstruction method images; the HPPI corporation for images of its TLP test equipment; and Chris O'Connor of UTI Inc. for transient latchup analysis.

I would like to thank the JEDEC organization's ESD committee.

This work was supported by the institutions that allowed me to teach and lecture at conferences, symposiums, industry, and universities; this gave me the motivation to develop the texts. I would like to thank for the years of support and the opportunity to provide lectures, invited talks, and tutorials at the International Physical and Failure Analysis (IPFA) in Singapore, the Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symposium, the International Reliability Physics Symposium (IRPS), and the Taiwan Electrostatic Discharge Conference (T-ESDC), International Conference on Solid State and Integrated Circuit Technology (ICSICT), and ASICON.

Finally, I am immensely thankful to the ESD Association office for the support in the area of publications, standards developments, and conference activities – Lisa, Christine, and Terry. I also thank the publisher and staff of John Wiley and Sons, for including the text ESD Testing: From Components to Systems as part of the ESD book series.

To my children, Aaron Samuel Voldman and Rachel Pesha Voldman, good luck to both of you in the future.

And Betsy H. Brown, for her support on this text…

And of course, my parents, Carl and Blossom Voldman.

B”H
Dr Steven H. Voldman
IEEE Fellow