Cover
Title Page
Preface
1. Overview
2. Key feature in relation to existing literature
1 Quantum mechanics
1. 1.1 Introduction to quantum mechanics
2. 1.2 Basic quantum physics problems
3. Reference
2 Basics of tunnelling
1. 2.1 Understanding tunnelling
2. 2.2 WKB approximation
3. 2.3 Landauer’s tunnelling formula
4. 2.4 Advanced tunnelling models
5. References
3 The tunnel FET
1. 3.1 Device structure
2. 3.2 Qualitative behaviour
3. 3.3 Types of TFETs
4. 3.4 Other steep subthreshold transistors
5. References
4 Drain current modelling of tunnel FET: the task and its challenges
1. 4.1 Introduction
2. 4.2 TFET modelling approach
3. 4.3 MOSFET modelling approach
4. References
5 Modelling the surface potential in TFETs
1. 5.1 The pseudo-2D method
2. 5.2 The variational approach
3. 5.3 The infinite series solution
4. 5.4 Extension of surface potential models to different TFET structures
5. 5.5 The effect of localised charges on the surface potential
6. 5.6 Surface potential in the depletion regions
7. 5.7 Use of smoothing functions in the surface potential models
8. References
6 Modelling the drain current
1. 6.1 Non-local methods
2. 6.2 Local methods
3. 6.3 Threshold voltage models
4. References
7 Device simulation using ATLAS
1. 7.1 Simulations using ATLAS
2. 7.2 Analysis of simulation results
3. 7.3 SOI MOSFET example
4. Reference
8 Simulation of TFETs
1. 8.1 SOI TFET
2. 8.2 Other tunnelling models
3. 8.3 Gate all around nanowire TFET
4. References
Index
End User License Agreement

List of Illustrations

Chapter 01
1. Figure 1.1 (a) Classically predicted electron pattern. It can be seen that interference fringes are experimentally observed, as opposed to the classically predicted pattern. This establishes the wave-like behaviour of electrons, (b) experimentally observed electron pattern.
2. Figure 1.2 Probability density of a quantum particle moving from left to right, plotted at different points of time (t₂>t₁>t₀).
3. Figure 1.3 Particle in a one-dimensional box.
4. Figure 1.4 Energy eigenfunctions of a particle in a one-dimensional box.
Chapter 02
1. Figure 2.1 (a) Emerging electromagnetic wave has negligible amplitude. (b) Emerging electromagnetic wave’s amplitude is attenuated, but not to negligible levels.
2. Figure 2.2 Tunnelling through a rectangular barrier.
3. Figure 2.3 (a) Regions divided by a potential barrier with no external bias. No empty states exist in Region B for electrons to tunnel. (b) Regions divided by a potential barrier with external bias. Empty states exist in Region B, to which electrons can now tunnel.
4. Figure 2.4 (a) Energy bands of a semiconductor under zero bias, with inset E–k diagrams. (b) Energy bands of a semiconductor with an electric field, with inset E–k diagrams. Non-local occurs, with the electron transitioning from the valence band maxima to the conduction band minima in the E–k diagram.
5. Figure 2.5 (a) Electrons from the conduction band of the n-region can tunnel traps having energy lower than the conduction band minima. (b) Electrons occupying traps having energy above the conduction band minima can tunnel to the conduction band [7].
6. Figure 2.6 Incorporation of density of states in the Hurkx model [7].
Chapter 03
1. Figure 3.1 Basic structure of a TFET.
2. Figure 3.2 Band diagram at the surface of a n-channel TFET in thermal equilibrium (i.e. at zero bias).
3. Figure 3.3 Band diagram along the surface of a TFET in the OFF-state (i.e. at V_GS = 0 V).
4. Figure 3.4 Band diagram along the surface of a TFET (a) at the beginning of the ON-state and (b) deep into the ON-state.
5. Figure 3.5 Band diagram along the surface of the TFET with increasing value of the gate voltage (V_GS) in the ON-state.
6. Figure 3.6 Band diagram along the surface of a TFET (a) for a zero gate voltage (V_GS) and a positive drain voltage (V_DS), (b) for a negative gate voltage (V_GS) and a positive drain voltage (V_DS), (c) for a negative gate voltage (V_GS) such that the valence band in the source gets aligned with the conduction band in the drain and a positive drain voltage (V_DS), (d) for a more negative gate voltage (V_GS) as compared to Figure 3.6 (c) and a positive drain voltage (V_DS) and (e) with an increasing negative value of the gate voltage (V_GS) and a positive drain voltage (V_DS).
7. Figure 3.7 Band diagram along the surface of a TFET for a fixed value of the gate voltage (V_GS) (in the ON-state) and different values of drain voltage (V_DS).
8. Figure 3.8 Transfer characteristics (I_D –V_GS) of an n-channel TFET (a) for a positive value of V_DS, showing different regions of operations, (b) showing the source–channel tunnelling (ON-state current) and drain–channel tunnelling (ambipolar current) and (c) for different values of V_DS.
9. Figure 3.9 Output characteristics (I_D–V_DS) of an n-channel TFET for different values of V_GS.
10. Figure 3.10 Output characteristics (I_D–V_DS) of an n-channel MOSFET for different values of V_GS.
11. Figure 3.11 Surface potential of a p-channel TFET and a p-channel MOSFET in the linear and the saturation regions of operation.
12. Figure 3.12 Band diagrams along the surface of an n-channel TFET with different values of source doping concentration.
13. Figure 3.13 Transfer characteristics of an n-channel TFET with different drain doping concentrations for a fixed drain voltage (V_DS).
14. Figure 3.14 Band diagram along the surface of an n-channel TFET for different values of the gate metal work function.
15. Figure 3.15 Transfer characteristics of an n-channel TFET with different values of the gate work function.
16. Figure 3.16 Gate leakage in a TFET through (a) SiO₂ and (b) HfO₂/SiO₂ gate stack [9].
17. Figure 3.17 Schematic of a p-channel SOI TFET.
18. Figure 3.18 Schematic of a p-channel double gate (DG) TFET.
19. Figure 3.19 Schematic of a p-channel dual material gate (DMG) TFET [10].
20. Figure 3.20 Comparison of the transfer characteristics of two single material gate (SMG) TFETs having different gate work functions to that of a DMG TFET.
21. Figure 3.21 Schematic of a p-channel n-p-n-p TFET (i.e. p-n-p-n TFET for an n-channel TFET).
22. Figure 3.22 Band diagram of a p-channel n-p-n-p TFET (i.e. p-n-p-n TFET for an n-channel TFET) along the surface in the ON-state.
23. Figure 3.23 Band diagram of a p-channel n-p-n-p TFET (i.e. p-n-p-n TFET for an n-channel TFET) along the surface with varying widths of the P⁺ pocket region.
24. Figure 3.24 Schematic of a charge plasma p-n-p-n TFET.
25. Figure 3.25 Schematic of (a) planar, (b) partially raised and (c) fully raised Ge-source TFETs. Dominant directions of tunnelling are shown by arrows [19].
26. Figure 3.26 (a) Schematic view of an n-channel heterojunction TFET. (b) Band diagram of the heterojunction TFET shown in (a) [20].
27. Figure 3.27 Schematic view of a p-channel ferroelectric TFET.
28. Figure 3.28 Comparison of the I_D–V_GS curves of a ferroelectric TFET with that of a MOSFET and a conventional TFET [21].
29. Figure 3.29 Schematic view of a gate all around (GAA) nanowire TFET.
30. Figure 3.30 Schematic view of a tri-gate (fin) TFET.
31. Figure 3.31 (a) Point tunnelling and (b) line tunnelling in a TFET.
Chapter 04
1. Figure 4.1 Schematic depicting the depletion region and the inversion layer charge in the channel of a TFET.
2. Figure 4.2 Electric field and along the surface of a TFET in the x- and the y-directions.
3. Figure 4.3 Schematic view of the TFET.
4. Figure 4.4 Comparison between the surface potential of the TFET shown in Figure 4.3 and that of an equivalent MOSFET.
5. Figure 4.5 Potential profile along the y-direction of the TFET.
6. Figure 4.6 Potential profile along the y-direction in a TFET in the body region showing the boundary conditions.
7. Figure 4.7 Potential profile at the surface along the x-direction of a TFET, showing the boundary conditions.
8. Figure 4.8 Tunnelling generation rate (G_btb) at the surface, along the x-direction of a TFET.
9. Figure 4.9 Surface potential profile at the surface, along the x-direction of a TFET, showing the shortest tunnelling length.
Chapter 05
1. Figure 5.1 Schematic view of a TFET.
2. Figure 5.2 Potential distribution along the x-direction of a TFET at the surface.
3. Figure 5.3 Potential distribution along the y-direction of a TFET.
4. Figure 5.4 Surface potential along the channel of a TFET.
5. Figure 5.5 Potential along the depth (y-direction) of a TFET.
6. Figure 5.6 Schematic of an n-channel TFET.
7. Figure 5.7 Surface potential along the channel of the TFET for different gate voltages.
8. Figure 5.8 Potential along the channel of the TFET at different depths (y) from the surface.
9. Figure 5.9 Variation in λ(y) with y for different values of T_Si [20].
10. Figure 5.10 Boundary conditions in a 2D solution space for the Laplace equation.
11. Figure 5.11 Boundary conditions for the potential distribution in a TFET.
12. Figure 5.12 Boundary conditions for the potential distribution in an SOI TFET.
13. Figure 5.13 Schematic of a p-channel double gate (DG) TFET.
14. Figure 5.14 Potential distribution along the y-direction in a DG TFET.
15. Figure 5.15 Schematic of a p-channel double gate (DG) TFET showing the axis of symmetry.
16. Figure 5.16 Boundary conditions for the potential distribution of a DG TFET.
17. Figure 5.17 Schematic of a p-channel gate all around (GAA) nanowire TFET.
18. Figure 5.18 Potential distribution along the radius of a GAA nanowire TFET.
19. Figure 5.19 (a) Schematic of a p-channel dual material gate (DMG) TFET. (b) Surface potential along the channel of a DMG TFET.
20. Figure 5.20 Boundary conditions for the potential distribution of a DMG TFET.
21. Figure 5.21 Schematic of a p-channel dual soi TFET showing the presence of localised charges at the si-sio₂ interface near the source side.
22. Figure 5.22 Schematic of an n-channel TFET showing source and drain depletion regions.
23. Figure 5.23 Variation in the mid-channel potential of an n-channel TFET with varying gate voltage (V_GS) [30].
Chapter 06
1. Figure 6.1 (a) Band diagram of an n-channel TFET at the surface in the ON-state. (b) Band diagram in the source–channel junction.
2. Figure 6.2 Band diagram in the source–channel junction of the TFET in the ON-state showing the tunnelling of an electron across the bandgap.
3. Figure 6.3 Tunnelling of an electron across in a linear potential profile.
4. Figure 6.4 Surface potential of a p-channel TFET in the ON-state.
5. Figure 6.5 Tunnelling generation rate (G_btb) at the surface along the channel of a TFET starting from the source–channel junction.
6. Figure 6.6 Tangent line l₁ to the G_btb curve. The shaded area is G₁.
7. Figure 6.7 Tangent line l₂ to the G_btb curve. The shaded area is G₂.
8. Figure 6.8 Tangent line l₃ to the G_btb curve. The shaded area is G₃.
9. Figure 6.9 Area common to the tangent lines l₁ and l₂, that is G_1d.
10. Figure 6.10 Area common to the tangent lines l₂ and l₃, that is G_2d.
11. Figure 6.11 Dependence of the gate threshold voltage on the drain voltage for an n-channel TFET.
12. Figure 6.12 Variation in the gate threshold voltage with the gate length for an n-channel TFET.
13. Figure 6.13 Dependence of the drain threshold voltage on the gate voltage for an n-channel TFET.
Chapter 07
1. Figure 7.1 Example of a 2D mesh grid in ATLAS.
2. Figure 7.2 Flow of information in ATLAS.
3. Figure 7.3 Example of regions of a device structure in ATLAS.
4. Figure 7.4 The DECKBUILD window.
5. Figure 7.5 Example of a log file in ATLAS.
6. Figure 7.6 Example of a structure file in ATLAS.
7. Figure 7.7 Schematic of the SOI MOSFET under study.
8. Figure 7.8 Mesh grid of the SOI MOSFET example.
9. Figure 7.9 Electrodes of the SOI MOSFET example.
10. Figure 7.10 The structure file of the SOI MOSFET example showing the different regions and the doping profile (in log scale) in the device.
11. Figure 7.11 The log file of the SOI MOSFET example showing the drain current (I_D) versus the gate voltage (V_GS) characteristics.
Chapter 08
1. Figure 8.1 Schematic of the SOI TFET under study.
2. Figure 8.2 Reproduction of experimental results [2, Figure 6(a)] to calibrate the tunnelling parameters [3].
3. Figure 8.3 Tunnelling generation rate at the silicon–oxide interface (i.e. at y = 0) along the channel (i.e. x-direction).
4. Figure 8.4 The structure file of the SOI TFET example showing the different regions and the doping profile (in log scale) in the device.
5. Figure 8.5 The structure file of the SOI TFET showing the potential plotted along a horizontal cutline made at the surface of the device (i.e. at y = 0).
6. Figure 8.6 The log file of the SOI TFET example showing the drain current (I_D) versus gate voltage (V_GS) characteristics.
7. Figure 8.7 Schematic view of the GAA nanowire TFET.
8. Figure 8.8 The structure file of the GAA nanowire TFET opened in TONYPLOT3D.

This edition first published 2017
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Library of Congress Cataloging-in-Publication Data

Names: Kumar, Mamidala Jagadesh, author. | Vishnoi, Rajat, author. | Pandey, Pratyush, author.
Title: Tunnel field-effect transistors (TFET) : modelling and simulations / Jagadesh Kumar Mamidala, Rajat Vishnoi and Pratyush Pandey.
Description: 1 | Hoboken : Wiley, 2016. | Includes bibliographical references and index.
Identifiers: LCCN 2016023165 (print) | LCCN 2016041464 (ebook) | ISBN 9781119246299 (hardback) | ISBN 9781119246282 (pdf) | ISBN 9781119246305 (epub)
Subjects: LCSH: Tunnel field-effect transistors. | Integrated circuits-Design and construction. | Nanostructured materials. | Low voltage integrated circuits. | BISAC: TECHNOLOGY & ENGINEERING / Electronics / Semiconductors.
Classification: LCC TK7871.95 .K86 2016 (print) | LCC TK7871.95 (ebook) | DDC 621.3815/284–dc23
LC record available at https://lccn.loc.gov/2016023165

A catalogue record for this book is available from the British Library.

Preface

Overview

Just as a human body is made up of millions of biological cells, an integrated circuit is made up of millions of transistors. Transistors are the basic building blocks of all modern electronic gadgets. Ever since the advent of CMOS circuits, the dimensions of the transistor have been continuously scaled down in order to pack more logic on to a silicon wafer and also to reduce power consumption in the circuits. In recent years, with mobile devices becoming popular, the search for low power devices with steep switching characteristics has become important. Highly scaled MOSFETs are rendered unsuitable for low power applications due to a thermal limit on their switching. Hence, the Tunnel Field Effect Transistor (TFET) is being explored extensively for low power applications. A TFET has a steep switching characteristic as it works on the phenomena of band-to-band tunnelling. Over the past few years, TFETs have been heavily researched by various notable groups in the field of semiconductor devices across the globe.

This book provides a comprehensive guide for those who are beginning their study on TFETs and also as a guide for those who wish to design integrated circuits based on TFETs. The book covers the essential physics behind the functioning of the TFETs and also the device modelling of TFETs, for the purpose of circuit design and simulation. It begins with studying the basic principles of quantum mechanics and then builds up to the physics behind the quantum mechanical phenomena of band-to-band tunnelling. This is followed by studying the basic functioning of TFETs and their different structural configurations. After explaining the functioning of TFETs, the book describes different approaches used by researchers for developing the drain current models for TFETs. Finally, to help new researchers in the field of TFETs, the book describes the process of carrying out numerical simulations of TFETs using the TCAD tool Silvaco ATLAS. Numerical simulations are helpful tools for studying the behaviour of any semiconductor device without getting into the complex process of fabrication and characterisation.

Key feature in relation to existing literature

This book is the first comprehensive literature on TFETs, which are very popular transistors and have been extensively studied in recent years; they are going to be important building blocks for low power solid state circuits in the future. It is a one-stop volume for studying TFETs for someone who has a basic knowledge of MOSFET physics. It covers the physics behind the phenomena of tunnelling as well as the device physics of TFETs. It also has a unique feature of describing device simulation along with device physics so as to enable readers to do further research on TFETs.

The presentation of the book is clear and accurate and is written in simple language. The book endeavours to explain different phenomena in the TFETs using simple and logical explanations so as to enable the reader to get a real feel for the functioning of the device. Also, each and every aspect of the TFET has been compared to that of the MOSFET so that the facts presented in the book make more sense to the entire semiconductor device fraternity and help in the integration of the TFET with the prevailing technology in the industry. The book also attempts to cover all the recent research articles published on TFETs so as to make sure that, along with covering the basics, it also covers state of the art work on TFETs.

Tunnel Field-Effect Transistors (TFET)

Modelling and Simulation

Preface

Overview

Key feature in relation to existing literature