Cover
Title
Copyright
Introduction
1. Dissipation Sources in Electronic Circuits
1. 1.1. Brief description of logic types
2. 1.2. Origins of heat dissipation in circuits
2. Thermodynamics and Information Theory
1. 2.1. Recalling the basics: entropy and information
2. 2.2. Presenting Landauer’s principle
3. 2.3. Adiabaticity and reversibility
3. Transistor Models in CMOS Technology
1. 3.1. Reminder on semiconductor properties
2. 3.2. Long- and short-channel static models
3. 3.3. Dynamic transistor models
4. Practical and Theoretical Limits of CMOS Technology
1. 4.1. Speed–dissipation trade-off and limits of CMOS technology
2. 4.2. Sub-threshold regimes
3. 4.3. Practical and theoretical limits in CMOS technology
5. Very Low Consumption at System Level
1. 5.1. The evolution of power management technologies
2. 5.2. Sub-threshold integrated circuits
3. 5.3. Near-threshold circuits
4. 5.4. Chip interconnect and networks
6. Reversible Computing and Quantum Computing
1. 6.1. The basis for reversible computing
2. 6.2. A few elements for synthesizing a function
3. 6.3. Reversible computing and quantum computing
7. Quasi-adiabatic CMOS Circuits
1. 7.1. Adiabatic logic gates in CMOS
2. 7.2. Calculation of dissipation in an adiabatic circuit
3. 7.3. Energy-recovery supplies and their contribution to dissipation
4. 7.4. Adiabatic arithmetic architecture
8. Micro-relay Based Technology
1. 8.1. The physics of micro-relays
2. 8.2. Calculation of dissipation in a micro-relay based circuit
Bibliography
Index
End User License Agreement

List of Illustrations

1. Dissipation Sources in Electronic Circuits
1. Figure 1.1. Boolean functions with one variable
2. Figure 1.2. Boolean functions with two variables
3. Figure 1.3. Example of a three-variable function
4. Figure 1.4. Boolean material architecture
5. Figure 1.5. Counter, a non-combinational function
6. Figure 1.6. Basic systems in sequential logic
7. Figure 1.7. The functioning of the traffic lights model
8. Figure 1.8. Logical diagram of traffic lights
9. Figure 1.9. General diagram customized for the traffic lights model
10. Figure 1.10. Sequential synchronous circuit
11. Figure 1.11. Latches and flip-flops
12. Figure 1.12. Pipelined and non-pipelined architecture types
13. Figure 1.13. Sequential pipelined system
14. Figure 1.14. Using switches to perform AND and OR functions
15. Figure 1.15. The complete AND function
16. Figure 1.16. Complementary logic
17. Figure 1.17. NMOS and PMOS transistors
18. Figure 1.18. NAND using CMOS technology
19. Figure 1.19. CMOS circuit and output capacitor
20. Figure 1.20. Simplified electric diagram of a CMOS gate
21. Figure 1.21. AND gate in pass-transistor technology
22. Figure 1.22. Differential pass-transistor logic
23. Figure 1.23. Transmission gate
24. Figure 1.24. Transmission gate functioning
25. Figure 1.25. Exclusive OR in Pass-Gate logic
26. Figure 1.26. NAND function in dynamic logic
27. Figure 1.27. Dynamic logic gate
28. Figure 1.28. A diagram that is not functional
29. Figure 1.29. DOMINO logic
30. Figure 1.30. Dissipation in a two-port device
31. Figure 1.31. RC circuit and heat dissipation
2. Thermodynamics and Information Theory
1. Figure 2.1. Microscopic states
2. Figure 2.2. System interaction with a thermostat and Boltzmann’s distribution
3. Figure 2.3. Irreversible gate
4. Figure 2.4. Two-state system
5. Figure 2.5. Binary register based on unique atoms or molecules
6. Figure 2.6. A factor two compression
7. Figure 2.7. The paradox of Maxwell’s demon
8. Figure 2.8. Verification of Landauer’s principle
9. Figure 2.9. Dissipation in a logically reversible transformation
10. Figure 2.10. Interconnect capacitance and “scaling”
11. Figure 2.11. Capacitor charge
12. Figure 2.12. Optimal and quasi-optimal solutions in a constant capacitance charge
13. Figure 2.13. Adiabatic charge of a capacitor when leakage is present
14. Figure 2.14. A logic gate with an adiabatic command
15. Figure 2.15. The Benett clocking principle
16. Figure 2.16. Incomplete pipeline
17. Figure 2.17. Operational adiabatic pipeline
18. Figure 2.18. Quasi-adiabatic gate
19. Figure 2.19. The reversible pipeline
3. Transistor Models in CMOS Technology
1. Figure 3.1. Silicon-bands diagram
2. Figure 3.2. Filling in the bands and the Fermi level
3. Figure 3.3. Bands and the notion of holes
4. Figure 3.4. Doped semiconductor
5. Figure 3.5. Doped semiconductors
6. Figure 3.6. Metal-oxide semiconductor structure
7. Figure 3.7. Calculating the inversion charge
8. Figure 3.8. The Lilienfield patents
9. Figure 3.9. NMOS transistor functioning
10. Figure 3.10. Transistor in CMOS technology
11. Figure 3.11. Calculating the concentrations in a transistor
12. Figure 3.12. Transistor saturation
13. Figure 3.13. Characteristic curves of a channel n transistor
14. Figure 3.14. Quasi-static transistor model
15. Figure 3.15. Small signals transistor model
4. Practical and Theoretical Limits of CMOS Technology
1. Figure 4.1. Integrated circuits
2. Figure 4.2. Inverter model and layout
3. Figure 4.3. Sectional view of the inverter
4. Figure 4.4. Interconnect and scaling
5. Figure 4.5. Characteristic function of dissipation in CMOS technology
6. Figure 4.6. Current in weak inversion
7. Figure 4.7. Example of a logic gate
8. Figure 4.8. Example of logic gates in a global architecture
9. Figure 4.9. Lambert function
10. Figure 4.10. Sub-threshold inverter
11. Figure 4.11. Estimating the variability of the threshold voltage as a function of the technological node
12. Figure 4.12. Planar transistor on an SOI substrate and a FinFET transistor
13. Figure 4.13. Theoretical model of a transistor
5. Very Low Consumption at System Level
1. Figure 5.1. Parallelism and active power
2. Figure 5.2. Parallelization in a data path
3. Figure 5.3. Predicting and reducing consumption
4. Figure 5.4. Transistor chain and sub-threshold current
5. Figure 5.5. MTCMOS architecture
6. Figure 5.6. Classic SRAM architecture
7. Figure 5.7. Eight-transistor SRAM cell
8. Figure 5.8. Constrained optimum
9. Figure 5.9. Examples of relative sensitivity depending on the energy (from MAR [MAR 10])
10. Figure 5.10. Connections in an integrated circuit
11. Figure 5.11. Links between gates
12. Figure 5.12. Interconnect with repeaters
13. Figure 5.13. Dissipated power in an adapted or unadapted link
6. Reversible Computing and Quantum Computing
1. Figure 6.1. Reversible and irreversible gates
2. Figure 6.2. Constructing a reversible gate with a width of 2
3. Figure 6.3. Control gate
4. Figure 6.4. Cascading two control gates
5. Figure 6.5. The conventions of reversible logic for a control gate
6. Figure 6.6. Control inverter
7. Figure 6.7. Toffoli gate
8. Figure 6.8. Feynman gate
9. Figure 6.9. Fredkin gate
10. Figure 6.10. Duplicating a signal and a fan-out
11. Figure 6.11. Sylow cascade
12. Figure 6.12. The “twiin circuit”
13. Figure 6.13. Synthesis of a reversible function
14. Figure 6.14. The synthhesis steps
15. Figure 6.15. The reversible copy
16. Figure 6.16. Controlled inverter boarding an irreversible function
17. Figure 6.17. Example of a majority gate
18. Figure 6.18. Truth table of a reversible adder
19. Figure 6.19. Synthesis of a reversible binary adder
20. Figure 6.20. A 4-bit reversible adder
21. Figure 6.21. Inverter controlled by a single control bit
22. Figure 6.22. Inverter controlled by two inputs
23. Figure 6.23. The signals in reversible adiabatic logic
24. Figure 6.24. Adiabatic command of a reversible circuit
25. Figure 6.25. Quantum adder
7. Quasi-adiabatic CMOS Circuits
1. Figure 7.1. Dissipation in a logic gate
2. Figure 7.2. Logic pipeline
3. Figure 7.3. NAND CMOS gate
4. Figure 7.4. Non-adiabatic case
5. Figure 7.5. “Bennet clocking”-type architecture
6. Figure 7.6. The adiabatic pipeline (example of an AND gate at the input)
7. Figure 7.7. CMOS architecture’s incompatibility with the adiabatic principle
8. Figure 7.8. ECRL buffer/inverter
9. Figure 7.9. Generic ECRL gate
10. Figure 7.10. PFAL inverter
11. Figure 7.11. General PFAL
12. Figure 7.12. The 2N-2N2P (left) inverter and the DCPAL (right) inverter
13. Figure 7.13. Comparison of different logic families [BHA 11]
14. Figure 7.14. Phase 2 in PFAL
15. Figure 7.15. Phase 3 in PFAL
16. Figure 7.16. Phase 4 in PFAL
17. Figure 7.17. Phase 1 in PFAL for the following event
18. Figure 7.18. Energy optimum in adiabatic logic
19. Figure 7.19. Sub-threshold adiabatic gate
20. Figure 7.20. Role of supplies in energy recovery
21. Figure 7.21. Capacitor-based energy recovery supply
22. Figure 7.22. Output voltage formation
23. Figure 7.23. Optimal number of steps in a capacitor-based generator
24. Figure 7.24. Different solutions for energy recovery supplies
25. Figure 7.25. Inductive energy recovery supply
26. Figure 7.26. 2N2P-type generator
27. Figure 7.27. Classic logic and adiabatic logic
28. Figure 7.28. Four-bit adiabatic adder
29. Figure 7.29. Complex exclusive OR gate with N inputs
8. Micro-relay Based Technology
1. Figure 8.1. Micro-relay with a suspended membrane (according to [KAM 11])
2. Figure 8.2. Characteristic curve of a micro-relay
3. Figure 8.3. Dynamic model of a nano-relay
4. Figure 8.4. Movement of the mobile structure according to the time [LEU 08]
5. Figure 8.5. A device in the plane
6. Figure 8.6. NEMIAC project’s particular design
7. Figure 8.7. Model for optimizing nano-relays
8. Figure 8.8. Micro-relay based adiabatic gate
9. Figure 8.9. Circuit without non-adiabatic dissipation
10. Figure 8.10. Circuit with non-adiabatic dissipation
11. Figure 8.11. OR gate with bistable micro-relays
12. Figure 8.12. “Dual-rail” adiabatic gate
13. Figure 8.13. Comparison of field-effect transistor-based adiabatic solutions with micro-relay based adiabatic solutions

List of Tables

1. Dissipation Sources in Electronic Circuits
1. Table 1.1. Table of transition between states
2. Table 1.2. Pipeline functioning
3. Table 1.3. Activity factor for the common gates
2. Thermodynamics and Information Theory
1. Table 2.1. Energy efficiency of the optimal solution
3. Transistor Models in CMOS Technology
1. Table 3.1. Contact potentials for common metals
2. Table 3.2. Transistor model parameters
4. Practical and Theoretical Limits of CMOS Technology
1. Table 4.1. Static energy and dynamic energy
5. Very Low Consumption at System Level
1. Table 5.1. Static current and inputs
6. Reversible Computing and Quantum Computing
1. Table 6.1. The truth table
2. Table 6.2. The truth table
8. Micro-relay Based Technology
1. Table 8.1. The main characteristics of the devices

Introduction

Energy efficiency is currently at the center of electronic and computer evolution. In fact, the objective of all three layers of information and communication technologies (i.e. high-performance servers and computers, mobile systems and connected objects) is to improve energy efficiency, meaning to compute more while consuming less. The costs of cooling systems’ centers need to be restricted, the autonomy of portable systems needs to be increased and autonomous objects capable of functioning only on the energy that they recover need to be invented.

In these three cases, the power measurements are very different: kilowatts for servers, watts for mobile systems and micro-watts for connected objects. However, the mechanism that creates heat is the same in all the three cases and is due to the Joule effect. Two sources of dissipation have been identified: the first is the energy dissipated during the operations of charging and discharging the active electronic circuit capacitances and the second is the energy dissipated by currents that circulate permanently from the supply source to the ground when the circuits are in the sub-threshold regime. Therefore, it is necessary to fully understand these two phenomena in order to identify the causes that create heat and the possible paths for improvement. This is the objective of the first two chapters, which analyze the logic families. Thus, there appear to be links between heat creation and whether or not information is lost in logical operations. Chapter 3 provides the physical foundations necessary for understanding how the CMOS technology components in current use work.

Electronics has been confronting this crucial problem since the 2000s, as contrary to the initial predictions, it is no longer possible to pair the decrease in transistor size with a decrease in supply voltage. Therefore, the density of the dissipated power does not stop growing in an integrated circuit. In Chapters 4 and 5, more and more sophisticated optimization techniques are described, which allow us to more or less restrict heat creation and energy consumption, but no solution seems to be capable of providing the longawaited benefits. The analysis carried out in this book shows that for the current circuit architecture, the limit is intrinsic to semiconductor-based technologies, and that significant improvements can only be made by throwing the circuit architecture and component technology into question again. In order to achieve these objectives, new solutions (adiabatic computing and nano-relay technology) are proposed and described in Chapters 7 and 8. Chapter 5 is dedicated to reversible computing, considered by some to be the only solution for achieving extremely weak dissipation levels. It is also an introduction to quantum computing, which can be considered as an extension of reversible computing.

In summary, this book is an introduction to new possible directions in the evolution of electronic and computing systems. New directions will allow these systems to move beyond concepts that are dictated mainly by research on speed (which explains how electronics has evolved from the 1950s to the 2000s), to concepts that are inspired by the research of excellent energy efficiency.