Cover

Table of Contents

Cover

Title Page

List of Figures

List of Tables

Preface

Chapter 1: Computer Fundamentals and Performance Evaluation

1.1 Overview of Computer Systems
1.2 Basic Structure of Computers
1.3 Improving Computer Performance
1.4 Hardware Description Languages
Exercises

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL

2.1 Logic Gates
2.2 Logic Circuit Design in Verilog HDL
2.3 CMOS Logic Gates
2.4 Four Levels/Styles of Verilog HDL
2.5 Combinational Circuit Design
2.6 Sequential Circuit Design
Exercises

Chapter 3: Computer Arithmetic Algorithms and Implementations

3.1 Binary Integers
3.2 Binary Addition and Subtraction
3.3 Binary Multiplication Algorithms
3.4 Binary Division Algorithms
3.5 Binary Square Root Algorithms
Exercises

Chapter 4: Instruction Set Architecture and ALU Design

4.1 Instruction Set Architecture
4.2 MIPS Instruction Format and Registers
4.3 MIPS Instructions and AsmSim Tool
4.4 ALU Design
Exercises

Chapter 5: Single-Cycle CPU Design in Verilog HDL

5.1 The Circuits Required for Executing an Instruction
5.2 Register File Design
5.3 Single-Cycle CPU Datapath Design
5.4 Single-Cycle CPU Control Unit Design
5.5 Test Program and Simulation Waveform
Exercises

Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL

6.1 Exceptions and Interrupts
6.2 Design of CPU with Exception and Interrupt Mechanism
6.3 The CPU Exception and Interrupt Tests
Exercises

Chapter 7: Multiple-Cycle CPU Design in Verilog HDL

7.1 Dividing Instruction Execution into Several Clock Cycles
7.2 Multiple-Cycle CPU Schematic and Verilog HDL Codes
7.3 Multiple-Cycle CPU Control Unit Design
7.4 Memory and Test Program
Exercises

Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL

8.1 Pipelining
8.2 Pipeline Hazards and Solutions
8.3 The Circuit of the Pipelined CPU and Verilog HDL Codes
8.4 Precise Interrupts/Exceptions in Pipelined CPU
8.5 Design of Pipelined CPU with Precise Interrupt/Exception
Exercises

Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL

9.1 IEEE 754 Floating-Point Data Formats
9.2 Converting between Floating-Point Number and Integer
9.3 Floating-Point Adder (FADD) Design
9.4 Floating-Point Multiplier (FMUL) Design
9.5 Floating-Point Divider (FDIV) Design
9.6 Floating-Point Square Root (FSQRT) Design
Exercises

Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL

10.1 CPU/FPU Pipeline Model
10.2 Design of Register File with Two Write Ports
10.3 Data Dependency and Pipeline Stalls
10.4 Pipelined CPU/FPU Design in Verilog HDL
10.5 Memory Modules and Pipelined CPU/FPU Test
Exercises

Chapter 11: Memory Hierarchy and Virtual Memory Management

11.1 Memory
11.2 Cache Memory
11.3 Virtual Memory Management and TLB Design
11.4 Mechanism of TLB-Based MIPS Memory Management
Exercises

Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL

12.1 Overall Structure of Caches and TLBs
12.2 Design of Circuits Related to Caches
12.3 Design of Circuits Related to TLB
12.4 Design of CPU with Caches and TLBs
12.5 Simulation Waveforms of CPU with Caches and TLBs
Exercises

Chapter 13: Multithreading CPU and Multicore CPU Design in Verilog HDL

13.1 Overview of Multithreading CPUs
13.2 Multithreading CPU Design
13.3 Overview of Multicore CPUs
13.4 Multicore CPU Design
Exercises

Chapter 14: Input/Output Interface Controller Design in Verilog HDL

14.1 Overview of Input/Output Interface Controllers
14.2 Error Detection and Correction
14.3 Universal Asynchronous Receiver Transmitter
14.4 PS/2 Keyboard/Mouse Interface Design
14.5 Video Graphics Array (VGA) Interface Design
14.6 Input/Output Buses
Exercises

Chapter 15: High-Performance Computers and Interconnection Networks

15.1 Category of High-Performance Computers
15.2 Shared-Memory Parallel Multiprocessor Systems
15.3 Inside of Interconnection Networks
15.4 Topological Properties of Interconnection Networks
15.5 Some Popular Topologies of Interconnection Networks
15.6 Collective Communications
15.7 Low-Node-Degree Short-Diameter Interconnection Networks
Exercises

Bibliography

Index

End User License Agreement

List of Illustrations

Chapter 1: Computer Fundamentals and Performance Evaluation

Figure 1.1 Computer system organization
Figure 1.2 Simplified structure of RISC CPU
Figure 1.3 Simplified structure of pipelined CPU
Figure 1.4 On-chip dedicated instruction cache and data cache
Figure 1.5 Simplified structure of a multithreading CPU
Figure 1.6 Simplified structure of a multicore CPU
Figure 1.7 Memory hierarchy
Figure 1.8 TLB maps virtual address to physical address
Figure 1.9 I/O interfaces in a computer system
Figure 1.10 Amdahl's Law examples
Figure 1.11 Trace-driven simulation
Figure 1.12 Execution-driven simulation
Figure 1.13 Supercomputer and interconnection network
Figure 1.14 Waveform of time counter

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL

Figure 2.1 Three basic gates and four common gates
Figure 2.2 Karnaugh map for a 2-to-1 multiplexer
Figure 2.3 Schematic diagram of a 2-to-1 multiplexer
Figure 2.4 Waveform of a 2-to-1 multiplexer
Figure 2.5 Schematic diagram of a CMOS inverter
Figure 2.6 Schematic diagram of NAND and NOR gates
Figure 2.7 Schematic diagram of AND and OR gates
Figure 2.8 Implementing a multiplexer using only NAND gates
Figure 2.9 Implementing a multiplexer using CMOS transistors
Figure 2.10 Schematic diagram of multiplexer using tri-state and ordinary gates
Figure 2.11 Schematic diagram of decoder with enable control
Figure 2.12 Decoder and encoder
Figure 2.13 Waveform of a 8-3 priority encoder
Figure 2.14 A 1-to-8 demultiplexer
Figure 2.15 Schematic diagram of 32-bit left shifter
Figure 2.16 Schematic diagram of 32-bit barrel shifter
Figure 2.17 Schematic diagram of a D latch
Figure 2.18 Waveform of a D latch
Figure 2.19 Schematic diagram of an academic D flip-flop
Figure 2.20 Waveform of an academic D flip-flop
Figure 2.21 Schematic diagram of an industry D flip-flop
Figure 2.22 Waveform of an industry D flip-flop
Figure 2.23 Schematic diagram of a D flip-flop with enable control
Figure 2.24 Schematic diagram of the JK latch
Figure 2.25 Schematic diagram of the JK flip-flop
Figure 2.26 Waveform of the JK flip-flop
Figure 2.27 Schematic diagram of the T latch
Figure 2.28 Schematic diagram of the T flip-flop
Figure 2.29 Waveform of the T flip-flop
Figure 2.30 Schematic diagram of a shift register
Figure 2.31 Schematic diagram of a FIFO of depth 4
Figure 2.32 Waveforms of FIFO4
Figure 2.33 A circular FIFO implemented with RAM
Figure 2.34 Waveforms of RAM-based FIFO
Figure 2.35 Two models of the general finite state machine
Figure 2.36 A counter with a seven-segment LED
Figure 2.37 Block diagram of a counter with a seven-segment LED
Figure 2.38 State transition diagram of the counter
Figure 2.39 Karnaugh map for next state of the counter
Figure 2.40 Karnaugh map for the output function of the counter
Figure 2.41 Schematic diagram of 3-bit D flip-flops
Figure 2.42 Schematic diagram of next state for the counter
Figure 2.43 Schematic diagram of output function for the counter
Figure 2.44 Schematic diagram of the counter with a seven-segment LED
Figure 2.45 Waveform of the up/down counter

Chapter 3: Computer Arithmetic Algorithms and Implementations

Figure 3.1 Bit's significances of a 16-bit unsigned binary number
Figure 3.2 Bit's significances of a 16-bit 2's complement signed number
Figure 3.3 Addition of two 4-bit numbers
Figure 3.4 Schematic diagram of the full adder
Figure 3.5 Schematic diagram of full adder (using XOR gates)
Figure 3.6 Waveform of the full adder
Figure 3.7 Schematic diagram of 4-bit ripple adder
Figure 3.8 Schematic diagram of a 4-bit adder/subtracter
Figure 3.9 Waveform of a 4-bit adder/subtracter
Figure 3.10 Four-bit carry-lookahead adder
Figure 3.11 Waveform of the carry-lookahead adder
Figure 3.12 Multiplication of two 8-bit signed numbers
Figure 3.13 Implementing a signed multiplier using NAND gates
Figure 3.14 Waveform of a signed multiplier
Figure 3.15 First level of the 8-bit Wallace tree
Figure 3.16 Adders for 7th bit in the 8-bit Wallace tree
Figure 3.17 Schematic diagram of the 8-bit Wallace tree
Figure 3.18 Waveform of the $c03-math-0275$ Wallace tree (partial product)
Figure 3.19 Waveform of $c03-math-0277$ Wallace tree (product)
Figure 3.20 Schematic diagram of a restoring divider
Figure 3.21 Waveform of a restoring divider
Figure 3.22 Schematic diagram of a nonrestoring divider
Figure 3.23 Waveform of a nonrestoring divider
Figure 3.24 Schematic diagram of the Goldschmidt divider
Figure 3.25 Waveform of the Goldschmidt divider
Figure 3.26 Schematic diagram of 32-bit Newton–Raphson divider
Figure 3.27 Waveform of the Newton–Raphson divider
Figure 3.28 Schematic diagram of a restoring square rooter
Figure 3.29 Waveform of the restoring square rooter
Figure 3.30 Schematic diagram of a nonrestoring square rooter
Figure 3.31 Waveform of a nonrestoring square rooter
Figure 3.32 Schematic diagram of the Goldschmidt square rooter
Figure 3.33 Waveform of the Goldschmidt square rooter
Figure 3.34 Schematic diagram of the Newton–Raphson square rooter
Figure 3.35 Waveform of the Newton–Raphson square rooter

Chapter 4: Instruction Set Architecture and ALU Design

Figure 4.1 ISA as an interface between software and hardware
Figure 4.2 Little endian and big endian
Figure 4.3 Data alignment in memory locations
Figure 4.4 Instruction architecture
Figure 4.5 MIPS instruction formats
Figure 4.6 Stack for function call
Figure 4.7 Pointer of a variable
Figure 4.8 AsmSim main window
Figure 4.9 AsmSim program editor window
Figure 4.10 AsmSim graphics console window
Figure 4.11 AsmSim graphics window output when executing fonts.s
Figure 4.12 A graph that will be represented with linked lists
Figure 4.13 Schematic diagram of ALU
Figure 4.14 Waveform of ALU

Chapter 5: Single-Cycle CPU Design in Verilog HDL

Figure 5.1 Clock and clock cycle
Figure 5.2 Block diagram of instruction fetch
Figure 5.3 Block diagram for R-format arithmetic and logic instructions
Figure 5.4 Block diagram for R-format shift instructions
Figure 5.5 Block diagram for I-format arithmetic and logic instructions
Figure 5.6 Block diagram for I-format load and store instructions
Figure 5.7 Block diagram for I-format branch instructions
Figure 5.8 Block diagram for J-format jump instruction
Figure 5.9 Block diagram for J-format jump-and-link instruction
Figure 5.10 Block diagram for R-format jump-register instruction
Figure 5.11 Symbol of the register file
Figure 5.12 Block diagram of 32-bit D flip-flops with enable control
Figure 5.13 Block diagram of thirty-two 32-bit registers
Figure 5.14 Block diagram of the register file
Figure 5.15 Using multiplexer for the next PC selection
Figure 5.16 Using a multiplexer for ALU A-input selection
Figure 5.17 Using a multiplexer for ALU B-input selection
Figure 5.18 Using a multiplexer for register file written data selection
Figure 5.19 Block diagram of a single-cycle CPU
Figure 5.20 Block diagram of single-cycle computer
Figure 5.21 Waveform 1 of a single-cycle CPU
Figure 5.22 Waveform 2 of a single-cycle CPU

Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL

Figure 6.1 Dealing with exceptions and interrupts
Figure 6.2 Cause register of CP0
Figure 6.3 Mechanism of vectored exception/interrupt
Figure 6.4 EPC contents for exceptions and interrupts
Figure 6.5 Status register of CP0
Figure 6.6 Interrupt nesting
Figure 6.7 Priority interrupt controller
Figure 6.8 Daisy chain for priority interrupts
Figure 6.9 Three registers related to exceptions and interrupts
Figure 6.10 Format of exception- and interrupt-related instructions
Figure 6.11 Block diagram of the single-cycle CPU with exceptions and interrupts
Figure 6.12 Waveform of overflow and system call exceptions
Figure 6.13 Waveform of unimplemented instruction exception and interrupt

Chapter 7: Multiple-Cycle CPU Design in Verilog HDL

Figure 7.1 Timing comparison of (a) single-cycle and (b) multiple-cycle CPUs
Figure 7.2 Block diagram of instruction fetch of an MC CPU
Figure 7.3 Block diagram of instruction decode of an MC CPU
Figure 7.4 Block diagram for jump instructions in an MC CPU
Figure 7.5 Block diagram for branch instructions in an MC CPU
Figure 7.6 Block diagram for computational instructions in an MC CPU
Figure 7.7 Block diagram for load and store instructions in an MC CPU
Figure 7.8 Block diagram of write back of an MC CPU
Figure 7.9 Block diagram of an MC CPU plus memory
Figure 7.10 Block diagram of a MC computer
Figure 7.11 State transition diagram of an MC CPU
Figure 7.12 Block diagram of the control unit of an MC CPU
Figure 7.13 Waveform of an MC CPU (lui instruction)
Figure 7.15 Waveform of an MC CPU (jr and sw instructions)
Figure 7.14 Waveform of an MC CPU (lw instruction)
Figure 7.16 Another state transition diagram of an MC CPU

Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL

Figure 8.1 Single-cycle CPU executing a load instruction
Figure 8.2 Timing comparison between the three types of CPUs
Figure 8.3 Pipeline instruction fetch (IF) stage
Figure 8.4 Pipeline instruction decode (ID) stage
Figure 8.5 Pipeline execution (EXE) stage
Figure 8.6 Pipeline memory access (MEM) stage
Figure 8.7 Pipeline write back (WB) stage
Figure 8.8 Structural hazards caused by an iterative divider
Figure 8.9 Writing result to the register file in the write back stage
Figure 8.10 Data hazard examples
Figure 8.11 Internal forwarding to the EXE stage
Figure 8.12 Internal forwarding to the ID stage
Figure 8.13 Data hazard with load instruction
Figure 8.14 Mechanism of internal forwarding and pipeline stall
Figure 8.15 Implementing pipeline stall and instruction cancellation
Figure 8.16 Pipeline stall causing an instruction to be executed twice
Figure 8.17 Determining whether a branch is taken or not taken
Figure 8.18 Delayed branch
Figure 8.19 Implementation of delayed branch with one delay slot
Figure 8.20 Return address of the function call instruction
Figure 8.21 Detailed circuit of the pipelined CPU
Figure 8.22 Waveforms of the pipelined CPU (call subroutine)
Figure 8.23 Waveforms of the pipelined CPU (pipeline stall)
Figure 8.24 Waveforms of the pipelined CPU (return from subroutine)
Figure 8.25 Three registers for implementing precise interrupt
Figure 8.26 Interrupt occurring in an ordinary case
Figure 8.27 Interrupt occurring when decoding the branch instruction
Figure 8.28 Interrupt occurring in the ID stage of delay slot
Figure 8.29 Execution of system call instruction
Figure 8.30 Unimplemented instruction exception
Figure 8.31 Overflow exception occurring in the ordinary case
Figure 8.32 Overflow exception occurring in the delay slot
Figure 8.33 Two exceptions that might be occurring in the same clock cycle
Figure 8.34 Pipeline stages of mfc0 and mtc0 instructions
Figure 8.35 Instruction formats of mfc0, mtc0, syscall, and eret
Figure 8.36 The circuit of pipelined CPU with precise interrupt
Figure 8.37 Exception waveforms of an unimplemented instruction
Figure 8.38 Exception waveforms of system call
Figure 8.39 Interrupt waveforms (a branch instruction is in the ID stage)
Figure 8.40 Exception waveforms of an arithmetic overflow

Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL

Figure 9.1 IEEE 754 format of a single-precision floating-point number
Figure 9.2 IEEE 754 format of a double-precision floating-point number
Figure 9.3 Waveform of f2i converter
Figure 9.4 Intel x86 FPU control word
Figure 9.5 Intel x86 FPU state word
Figure 9.6 Waveform of an i2f converter
Figure 9.7 Shifting to the right by at most 26 bits is enough
Figure 9.8 Block diagram of a floating-point adder
Figure 9.9 Waveform of the floating-point adder
Figure 9.10 Increasing exponent caused by rounding
Figure 9.11 Special cases of floating-point additions/subtractions
Figure 9.12 Block diagram of a pipelined floating-point adder
Figure 9.13 Waveform of the pipelined floating-point adder
Figure 9.14 Block diagram of the floating-point multiplier
Figure 9.15 Schematic diagram of the 24-bit Wallace tree
Figure 9.16 Waveform of the floating-point multiplier
Figure 9.17 Block diagram of pipelined floating-point multiplier
Figure 9.18 Waveform of the pipelined floating-point multiplier
Figure 9.19 Block diagram of the floating-point divider
Figure 9.20 Pipeline stages of the floating-point divider
Figure 9.21 Schematic diagram of the 24-bit Newton–Raphson divider
Figure 9.22 Stall caused by the division instruction
Figure 9.23 Waveform of the floating-point divider
Figure 9.24 Block diagram of the floating-point square root
Figure 9.25 Pipeline stages of the floating-point square root
Figure 9.26 Block diagram of the Newton–Raphson square rooter
Figure 9.27 Stall caused by the square root instruction
Figure 9.28 Waveform of the square root of a normalized float number
Figure 9.29 Waveform of the square root of a denormalized float number

Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL

Figure 10.1 Pipeline models of the IU and the floating-point unit
Figure 10.2 Unpipelined and fully pipelined implementations
Figure 10.3 Stall signal for floating-point division and square root instructions
Figure 10.4 Unified floating-point pipeline model
Figure 10.5 Register file requiring two write ports
Figure 10.6 Schematic diagram of a register file with two write ports
Figure 10.7 Baseline diagram of IU and FPU
Figure 10.8 No-stall case for floating-point data hazard
Figure 10.9 Block diagram of forwarding floating-point data
Figure 10.10 One-cycle stall case for floating-point data hazard
Figure 10.11 Two-cycle stall case for floating-point data hazard
Figure 10.12 Block diagram for floating-point load and store instructions
Figure 10.13 Data hazard with floating-point load
Figure 10.14 Block diagram for forwarding memory data
Figure 10.15 One-cycle stall caused by floating-point load
Figure 10.16 Forwarding floating-point data to the instruction decode stage
Figure 10.17 Forwarding floating-point data to the execution stage
Figure 10.18 One-cycle stall caused by floating-point store
Figure 10.19 Block diagram of forwarding for floating-point load and store
Figure 10.20 Pipeline stalls caused by floating-point division and square root
Figure 10.21 Block diagram of CPU with one IU and one FPU
Figure 10.22 Block diagram of the floating-point unit
Figure 10.23 Block diagram of the integer unit
Figure 10.24 Waveform 1 of CPU/FPU (lwc1, add.s, and sub.s)
Figure 10.25 Waveform 2 of CPU/FPU (sub.s, mul.s, mul.s, and swc1)
Figure 10.26 Waveform 3 of CPU/FPU (div.s, sqrt.s, and sqrt.s)
Figure 10.27 Simple superscalar pipelines

Chapter 11: Memory Hierarchy and Virtual Memory Management

Figure 11.1 Demonstrating SRAM implementation
Figure 11.2 Static RAM cell
Figure 11.3 Dynamic RAM and DRAM cell
Figure 11.4 Read-only memory
Figure 11.5 Comparison of CAM and RAM
Figure 11.6 Structure of a content-addressable memory
Figure 11.7 Content-addressable memory cell
Figure 11.8 Cache or TLB implemented with a CAM and a RAM
Figure 11.9 (a) Asynchronous DRAM and (b) synchronous DRAM
Figure 11.10 Memory hierarchy
Figure 11.11 Block diagram of direct mapping cache
Figure 11.12 Block diagram of a fully associative mapping cache
Figure 11.13 Block diagram of set-associative mapping cache
Figure 11.14 LRU counter changes on cache misses and hits
Figure 11.15 Cache in between the CPU and the main memory
Figure 11.16 Block diagram of the write-through cache
Figure 11.17 Waveform of data cache read
Figure 11.18 Waveform of data cache write
Figure 11.19 Two processes residing in main memory
Figure 11.20 Concept of virtual memory management
Figure 11.21 Memory management by segmentation
Figure 11.22 External fragmentation in segmentation management
Figure 11.23 Memory management by paging
Figure 11.24 Two-level paging management
Figure 11.25 Segmentation and paging management
Figure 11.26 Block diagram of TLB using CAM
Figure 11.27 Implementation of an eight-entry TLB
Figure 11.28 Schematic diagram of TLB
Figure 11.29 Waveform 1 of an eight-entry TLB (tlbwi)
Figure 11.30 Waveform 2 of an eight-entry TLB (tlbwr)
Figure 11.31 Conditions for cache and TLB accesses in parallel
Figure 11.32 MIPS virtual memory space mapping
Figure 11.33 Contents of MIPS TLB entry
Figure 11.34 Page sizes and format of virtual address
Figure 11.35 Block diagram of TLB-based address translation
Figure 11.36 Page sizes and format of physical address
Figure 11.37 CPU manipulating TLB through CP0 registers
Figure 11.38 MIPS TLB manipulation registers of CP0
Figure 11.39 The meaning of wired register
Figure 11.40 Formats of TLB manipulating instructions
Figure 11.41 Four-way interleaved memory
Figure 11.42 Read timing of four-way interleaved memory

Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL

Figure 12.1 Dedicated TLBs and caches for instructions and data
Figure 12.2 Block diagram of instruction cache
Figure 12.3 Waveform of instruction cache miss
Figure 12.4 Waveform of instruction cache hit
Figure 12.5 Arbitrating competing requests for memory access
Figure 12.6 (a) Multiplexer and (b) demultiplexer
Figure 12.7 Waveform of arbitrating requests for memory access
Figure 12.8 Pipeline stall caused by cache misses
Figure 12.9 Waveform of pipeline stall caused by cache misses
Figure 12.10 Signals of instruction TLB and data TLB
Figure 12.11 TLB-related CP0 registers
Figure 12.12 ITLB miss in ordinary case
Figure 12.13 ITLB miss in delay slot
Figure 12.14 DTLB miss in the ordinary case
Figure 12.15 DTLB miss in delay slot
Figure 12.16 Cancel instructions due to DTLB miss
Figure 12.17 Block diagram of CPU with dedicated caches and TLBs
Figure 12.18 Waveform of initializing ITLB
Figure 12.19 Waveform of dealing with DTLB miss exception
Figure 12.20 Waveforms of returning from exception and cache hits

Chapter 13: Multithreading CPU and Multicore CPU Design in Verilog HDL

Figure 13.1 Multithreading and multicore CPUs
Figure 13.2 Basic concept of multithreading
Figure 13.3 Sequential multithreading and parallel multithreading
Figure 13.4 Organization of a multithreading CPU
Figure 13.5 Block diagram of a two-thread CPU
Figure 13.6 Schematic circuit of thread selection
Figure 13.7 Block diagram of multithreading CPU with two IUs and one FPU
Figure 13.8 Waveform of the multithreading CPU (lwc1, sub.s, and add.s)
Figure 13.9 Waveform of the multithreading CPU (div.s, sqrt.s, and sqrt.s)
Figure 13.10 Various multicore CPUs
Figure 13.11 Cache architecture in multicore CPUs
Figure 13.12 Block diagram of a dual-core CPU
Figure 13.13 Block diagram of memory access arbitration
Figure 13.14 Waveform of a dual-core CPU (caches miss)
Figure 13.15 Waveform of a dual-core CPU (caches hit)

Chapter 14: Input/Output Interface Controller Design in Verilog HDL

Figure 14.1 Relationship between memory space and I/O space
Figure 14.2 I/O polling and I/O interrupt
Figure 14.3 Direct memory access
Figure 14.4 (a) Synchronous and (b) asynchronous buses
Figure 14.5 Data and parity check bits of Hamming code
Figure 14.6 Calculating parity check bits
Figure 14.7 Data and parity check bits of extended Hamming code
Figure 14.8 Example of a polynomial division circuit
Figure 14.9 CRC calculation circuit
Figure 14.10 Waveform of the CRC calculation circuit
Figure 14.11 Waveform of CRC-32-IEEE calculation circuit
Figure 14.12 Data frame format of UART
Figure 14.13 Connection between two UARTs
Figure 14.14 Timing of the UART receiver
Figure 14.15 Sampling clock of UART receiver
Figure 14.16 Timing of UART sender
Figure 14.17 Sending clock of UART sender
Figure 14.18 Double buffers for receiver and transmitter in a UART
Figure 14.19 Waveform of UART (sending and receiving e1)
Figure 14.20 Waveform of UART (sending and receiving 55)
Figure 14.21 Data frame format of a PS/2 keyboard
Figure 14.22 Waveform of a PS/2 keyboard
Figure 14.23 Data frame contents of a PS/2 mouse
Figure 14.24 PS/2 keyboard/mouse connect
Figure 14.25 Timing of PS/2 mouse control signals
Figure 14.26 VGA display
Figure 14.27 HS/VS timing of a standard VGA
Figure 14.28 Signals of VGA interface controller
Figure 14.29 Waveform 1 of the VGA interface controller (first pixel)
Figure 14.30 Waveform 2 of the VGA interface controller (one frame)
Figure 14.31 Graphics mode and text mode of VGA
Figure 14.32 ASCII font example
Figure 14.33 Character address and font address
Figure 14.34 CPU $c14-math-0165$ RAMs $c14-math-0166$ font table $c14-math-0167$ VGA $c14-math-0168$ PS/2
Figure 14.35 Flowchart for dealing with keys
Figure 14.36 I2C serial bus
Figure 14.37 I2C bus signals
Figure 14.38 Start bit and stop bit of I2C bus
Figure 14.39 ACK of I2C bus
Figure 14.40 Data transfer on I2C bus
Figure 14.41 I2C write, read, and combined transfer
Figure 14.42 A method for generating I2C signals
Figure 14.43 I2C controller and its state transition diagram
Figure 14.44 I2C bus communication waveform
Figure 14.45 CPU $c14-math-0176$ RAMs $c14-math-0177$ font table $c14-math-0178$ VGA $c14-math-0179$ I2C EEPROM
Figure 14.46 I2C EEPROM write
Figure 14.47 I2C EEPROM read
Figure 14.48 Waveform of I2C EEPROM write
Figure 14.49 Waveform of I2C EEPROM read
Figure 14.50 Signals of the PCI bus
Figure 14.51 Timing of PCI bus read
Figure 14.52 Timing of PCI bus write
Figure 14.53 PCI memory example
Figure 14.54 Next state signal for PCI controller
Figure 14.55 Waveform of PCI bus write
Figure 14.56 Waveform of PCI bus read

Chapter 15: High-Performance Computers and Interconnection Networks

Figure 15.1 Communications in high-performance computers
Figure 15.2 Architecture of a symmetric multiprocessor system
Figure 15.3 Architecture of a distributed shared memory system
Figure 15.4 Full bitmap in directory-based cache coherency protocols
Figure 15.5 Doubly linked list in directory-based cache coherency protocols
Figure 15.6 Switches and cables in interconnection networks
Figure 15.7 An $c15-math-0007$ crossbar switch
Figure 15.8 An $c15-math-0008$ buffered crossbar switch
Figure 15.9 Implementation of crossbar
Figure 15.10 Crossbar with self-routing function
Figure 15.11 Ring and complete graph topologies
Figure 15.12 Mesh topology
Figure 15.13 Torus topology
Figure 15.14 Hypercube topology
Figure 15.15 Tree and fat-tree topologies
Figure 15.16 One-to-all broadcast in a hypercube
Figure 15.17 All-to-all broadcast in a hypercube
Figure 15.18 One-to-all personalized communication in a hypercube
Figure 15.19 All-to-all personalized communication in a hypercube
Figure 15.20 Cube-connected cycles
Figure 15.21 Hierarchical cubic network
Figure 15.22 Origin 2000 of three and four dimensions
Figure 15.23 Cray Router in 5D Origin 2000 (128 CPUs)
Figure 15.24 Node address format of a dual-cube
Figure 15.25 Dual-cube DC(2)
Figure 15.26 Implementing Origin 2000 with a dual-cube (512 CPUs)
Figure 15.27 Node address format of an m-cube oriented metacube
Figure 15.28 Metacube MC(2,2)
Figure 15.29 Node address format of a k-cube-oriented metacube
Figure 15.30 A k-cube-oriented metacube MC(1,2)
Figure 15.31 A k-cube-oriented metacube MC(2,1)
Figure 15.32 Recursive construction of RDN
Figure 15.33 Recursive dual-net RDN(4,1)
Figure 15.34 Recursive dual-net RDN(4,2)

List of Tables

Chapter 1: Computer Fundamentals and Performance Evaluation

Table 1.1 Category of instruction set architecture
Table 1.2 Some base units

Chapter 2: A Brief Introduction to Logic Circuits and Verilog HDL

Table 2.1 Outputs of seven gates (truth table)
Table 2.2 Truth Table of a 1-bit 2-to-1 multiplexer
Table 2.3 Truth Table of a 3-8 decoder
Table 2.4 Truth Table of an 8-3 encoder
Table 2.5 Truth Table of an 8-3 priority encoder
Table 2.6 State transition Table of the counter

Chapter 3: Computer Arithmetic Algorithms and Implementations

Table 3.1 Relationship between hexadecimal numbers and binary numbers
Table 3.2 The values of 4-bit binary numbers at different representations
Table 3.3 Truth Table of a full adder
Table 3.4 Eight-bit carry-lookahead adder
Table 3.5 Simplifying the two LSB calculation
Table 3.6 Cycles required by the Goldschmidt and Newton–Raphson algorithms

Chapter 4: Instruction Set Architecture and ALU Design

Table 4.1 Operand types
Table 4.2 Code examples of instruction architectures
Table 4.3 MIPS general-purpose registers
Table 4.4 Twenty MIPS integer instructions
Table 4.5 Some MIPS pseudo-instruction examples
Table 4.6 Code sequences for unimplemented instructions
Table 4.7 MIPS instructions related to interrupt/exception, TLB, and FP

Chapter 5: Single-Cycle CPU Design in Verilog HDL

Table 5.1 Instruction decode
Table 5.2 Control signals of single-cycle CPU
Table 5.3 Truth Table of the control signals

Chapter 6: Exceptions and Interrupts Handling and Design in Verilog HDL

Table 6.1 ExcCode field of the MIPS Cause register
Table 6.2 Definition of ExcCode and interrupt mask
Table 6.3 Overflow on signed add and subtract

Chapter 7: Multiple-Cycle CPU Design in Verilog HDL

Table 7.1 Clock cycles required by instructions
Table 7.2 Truth Table of next state function
Table 7.3 Truth Table of control signals

Chapter 8: Design of Pipelined CPU with Precise Interrupt in Verilog HDL

Table 8.1 Stage where exception or interrupt may occur
Table 8.2 Writing EPC on exception or interrupt

Chapter 9: Floating-Point Algorithms and FPU Design in Verilog HDL

Table 9.1 Examples of converting a float to an integer
Table 9.2 Results of operations on two infinity numbers
Table 9.3 FP rounding examples
Table 9.4 Fraction increment when rounding
Table 9.5 Example results of floating-point multiplications

Chapter 10: Design of Pipelined CPU with FPU in Verilog HDL

Table 10.1 Seven instructions related to the floating-point unit
Table 10.2 Data transfer and data conversion instructions

Chapter 11: Memory Hierarchy and Virtual Memory Management

Table 11.1 Combinations of write policies and allocate strategies
Table 11.2 Two processes that have the same virtual addresses
Table 11.3 Cache coherency attributes
Table 11.4 IDT79RC32355 cache coherency attributes
Table 11.5 Mask values in PageMask register

Chapter 12: Design of Pipelined CPU with Caches and TLBs in Verilog HDL

Table 12.1 Address mapping of the MIPS architecture
Table 12.2 Return address for EPC

Chapter 13: Multithreading CPU and Multicore CPU Design in Verilog HDL

Table 13.1 Method of thread selection
Table 13.2 Arbitration of memory accesses
Table 13.3 Cache coherence problem in multicore CPUs
Table 13.4 Cache block states for cache coherence

Chapter 14: Input/Output Interface Controller Design in Verilog HDL

Table 14.1 CRC calculation example
Table 14.2 Polynomial division operations in first three cycles
Table 14.3 Common CRC generator polynomials
Table 14.4 Keyboard make code and break code examples
Table 14.5 Address of I2C bus master controller
Table 14.6 C/BE bus command definitions

Chapter 15: High-Performance Computers and Interconnection Networks

Table 15.1 Topological properties of popular interconnection networks
Table 15.2 Types of collective communications
Table 15.3 Three cases of dual-cube routing
Table 15.4 Number of nodes in metacubes
Table 15.5 Cost ratio comparison of symmetric interconnection networks
Table 15.6 Topological properties of interconnection networks

This edition first published 2015

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