reading

Cover
Title Page
Copyright
About the Author
Preface
Chapter 1: SiP Design and Simulation Platform
1. 1.1 From package to SiP
2. 1.2 The development of mentor SiP design technology
3. 1.3 The mentor SiP design and simulation platform
4. 1.4 The introduction of the finished project
Chapter 2: Introduction to Package
1. 2.1 Definition and function of package
2. 2.2 Development of packaging technology
3. 2.3 SiP and Related Technologies
4. 2.4 The development of the package market
5. 2.5 Package manufacturers
6. 2.6 Bare chip suppliers
Chapter 3: The SiP Production Process
1. 3.1 BGA: The mainstream SiP package form
2. 3.2 The SiP package production process
3. 3.3 Three key elements of SiP
Chapter 4: New Package Technologies
1. 4.1 TSV (Through Silicon Via) technology
2. 4.2 Integrated passive device (IPD) technology
3. 4.3 Package on package (PoP) technology
4. 4.4 Apple A8 processor – an example of a PoP product
Chapter 5: SiP Design and Simulation Flow
1. 5.1 SiP design and simulation flow
2. 5.2 Design and simulation process in Mentor EE Flow
Chapter 6: Central Library
1. 6.1 The structure of the central library
2. 6.2 Introduction to the Dashboard
3. 6.3 Schematic symbol creation
4. 6.4 Bare chip cell creation
5. 6.5 BGA cell creation
6. 6.6 Part creation
7. 6.7 Create cell via part
Chapter 7: Schematic Input
1. 7.1 Netlist input
2. 7.2 Basic schematic input
3. 7.3 Schematic input based on DxDataBook
Chapter 8: Multi-board Project Management and Concurrent Schematic Design
1. 8.1 Multi-board project management
2. 8.2 Concurrent schematic design
Chapter 9: Layout Creation and Setting
1. 9.1 Create layout template
2. 9.2 Create layout project
3. 9.3 Layout-related setup and operation
4. 9.4 Substrate layout
5. 9.5 eDxD view
6. 9.6 Input Chinese characters in layout
Chapter 10: Constraint Rules Management
1. 10.1 CES – Constraint Editor System
2. 10.2 Scheme
3. 10.3 Define layer stackup and parameters
4. 10.4 Net Class
5. 10.5 Clearance rules
6. 10.6 Constraint class
7. 10.7 Update CES data with layout
Chapter 11: Wire Bond Design
1. 11.1 Wire bond overview
2. 11.2 Bond wire model
3. 11.3 Wire bond toolbar
Chapter 12: Cavity and Chip Stack Design
1. 12.1 Cavity
2. 12.2 Chip stack
Chapter 13: Flip Chip and RDL Design
1. 13.1 The concept and characteristics of flip chip
2. 13.2 The RDL concept
3. 13.3 RDL design
4. 13.4 Flip chip design
Chapter 14: Route and Plane
1. 14.1 Routing
2. 14.2 Plane
Chapter 15: Embedded Passives Design
1. 15.1 The development of embedded technology
2. 15.2 Process and material for embedded passives
3. 15.3 Resistor and capacitor automatic synthesis
Chapter 16: RF Circuit Design
1. 16.1 RF SiP Technology
2. 16.2 Mentor RF design flow
3. 16.3 RF schematic design
4. 16.4 RF parameter transfer between schematic and layout
5. 16.5 RF layout design
6. 16.6 Connect RF simulation tools and transfer data
Chapter 17: Concurrent Layout Design
1. 17.1 Concurrent layout design technology – Xtreme
2. 17.2 Xtreme configuration
3. 17.3 Start Xtreme concurrent design
4. 17.4 Matters to note in Xtreme
Chapter 18: 3D Real-time DRC
1. 18.1 Wire Model Editor 3D display and DRC
2. 18.2 3D Viewer display and DRC
Chapter 19: Design Review
1. 19.1 Online DRC
2. 19.2 Batch DRC
3. 19.3 Review hazards
4. 19.4 Verify design library
Chapter 20: Manufacturing Data Output
1. 20.1 Drill and Gerber data output
2. 20.2 Other Manufacturing Data Output
Chapter 21: SiP Simulation Technology
1. 21.1 SiP simulation technology overview
2. 21.2 Signal integrity simulation
3. 21.3 Power integrity simulation
4. 21.4 Thermal analysis
5. 21.5 EMI/EMC Analysis
6. 21.6 Mixed-signal simulation introduction
Reference Materials
Postscript and Thanks
Index
End User License Agreement

List of Illustrations

Chapter 1: SiP Design and Simulation Platform
1. Figure 1.1 Three different kinds of package.
2. Figure 1.2 Evolution from IC package and MCM to SiP.
3. Figure 1.3 The relationship between IC bare chips, SiP package and the PCB board-level system.
4. Figure 1.4 SiP is receiving attention from a wide range of areas.
5. Figure 1.5 Size and power consumption comparison between PCB and SiP.
6. Figure 1.6 Development of the Mentor SiP platform.
7. Figure 1.7 Mentor SiP/MCM/advanced package/PCB design and simulation platform.
8. Figure 1.8 Mentor EE Flow supported platforms and processors.
9. Figure 1.9 One project manages multiple designs, and realizes SiP and PCB collaborative design.
10. Figure 1.10 The six core design functions of Mentor SiP layout.
11. Figure 1.11 Chip stacks and multi-step cavity.
12. Figure 1.12 Mentor bond wire model.
13. Figure 1.13 Interactive 3D real-time DRC.
14. Figure 1.14 Expedition supports four kinds of EP resistor and three kinds of EP capacitor.
15. Figure 1.15 RF design data and RF parameter transfer.
16. Figure 1.16 Blind and buried via setup and application.
17. Figure 1.17 Sketch of Xtreme concurrent team design.
18. Figure 1.18 Screenshots of HyperLynx SI and PI.
19. Figure 1.19 Snapshot of HyperLynx Thermal analysis.
20. Figure 1.20 One of the finished customer projects using the Mentor SiP platform.
Chapter 2: Introduction to Package
1. Figure 2.1 A typical package structure.
2. Figure 2.2 The relationship between chip and package is like the human brain and torso.
3. Figure 2.3 Common package types.
4. Figure 2.4 Development trends in electronic packaging technology.
5. Figure 2.5 Diagram of Moore's law.
6. Figure 2.6 Typical SiP structure diagram.
7. Figure 2.7 Comparison of development time and development cost in SoC and SiP.
8. Figure 2.8 Three kinds of chip stacking.
9. Figure 2.9 Two kinds of embedded technologies.
10. Figure 2.10 IPD technology.
11. Figure 2.11 TSV technology.
12. Figure 2.12 PoP technology.
13. Figure 2.13 Package market share in 2009.
14. Figure 2.14 The proportion of SiP applications in different fields in 2005 and 2010.
Chapter 3: The SiP Production Process
1. Figure 3.1 Wire Bonding-BGA and Flip Chip-BGA.
2. Figure 3.2 CBGA and CCGA.
3. Figure 3.3 WB-BGA and FC-BGA manufacture process.
4. Figure 3.4 WB-BGA packaging manufacture process sketch map.
5. Figure 3.5 Flip Chip-BGA packaging manufacture process sketch map.
6. Figure 3.6 Hybrid-technology SiP manufacture process.
7. Figure 3.7 HDI substrate cross section.
Chapter 4: New Package Technologies
1. Figure 4.1 TSV sketch map.
2. Figure 4.2 TSV micrograph.
3. Figure 4.3 By the year 2018, 58% of 3D package will use TSV mode.
4. Figure 4.4 IPD sample.
5. Figure 4.5 Four kinds of integrated IPD package.
6. Figure 4.6 Comparison of circuit before and after using IPD.
7. Figure 4.7 IPD market sales data.
8. Figure 4.8 The typical structure of PoP package.
9. Figure 4.9 Apple iPhone 6 and iPhone 6 plus.
10. Figure 4.10 A8 processor and iPhone 6 mainboard.
11. Figure 4.11 A8 processor structure diagram and cross section.
Chapter 5: SiP Design and Simulation Flow
1. Figure 5.1 SiP design and simulation flow chart.
2. Figure 5.2 SiP design and simulation environment in EE Flow.
3. Figure 5.3 SiP schematic design.
4. Figure 5.4 Typical distribution of power, GND and signal pins.
5. Figure 5.5 Blind and buried via setup and wire bonding setup.
6. Figure 5.6 Expedition network automatic optimization.
7. Figure 5.7 Completed SiP design (2D Figure and 3D figure).
8. Figure 5.8 Export design to HyperLynx for simulation.
9. Figure 5.9 The results of thermal analysis.
Chapter 6: Central Library
1. Figure 6.1 The structure of the Mentor central library.
2. Figure 6.2 The relationship of the central library, schematic and layout.
3. Figure 6.3 Dashboard interface.
4. Figure 6.4 Active project.
5. Figure 6.5 Toolboxes.
6. Figure 6.6 Library Manager user interface.
7. Figure 6.7 Create a new central library.
8. Figure 6.8 Boarders, built-in and Globals partitions created by the system.
9. Figure 6.9 Create new partition.
10. Figure 6.10 Create symbol via Symbol Wizard.
11. Figure 6.11 Properties definition for symbol.
12. Figure 6.12 Set the pin properties of symbol.
13. Figure 6.13 Edit symbol properties in Excel.
14. Figure 6.14 Copy-and-paste to create a symbol.
15. Figure 6.15 The completion of symbol Sym1.
16. Figure 6.16 Create a new pad.
17. Figure 6.17 Create Custom Pads and Drill Symbols.
18. Figure 6.18 Create die pad.
19. Figure 6.19 Create new cell partition SiP_CELL.
20. Figure 6.20 Create new cell DIE_CELL1.
21. Figure 6.21 Create cell and edit cell properties.
22. Figure 6.22 First delete all pins in the Place Pins interface.
23. Figure 6.23 Import the die pin definition file via Die Wizard.
24. Figure 6.24 The outline and reference options of Add Tools.
25. Figure 6.25 Bare die cell.
26. Figure 6.26 Create round pad in Pads tab of Padstack Editor.
27. Figure 6.27 Create a BGA padstack in Padstack Editor.
28. Figure 6.28 Use the thermal definition from padstack of central library.
29. Figure 6.29 BGA_cell properties settings.
30. Figure 6.30 Specify Padstack Name and rename BGA pins.
31. Figure 6.31 Rename the BGA Pin# and set placement parameters.
32. Figure 6.32 Delete the pins in the middle of cavity.
33. Figure 6.33 Prompt to update pin number information.
34. Figure 6.34 Renaming pin numbers using mouse movement.
35. Figure 6.35 View the pin properties and different process layers.
36. Figure 6.36 BGA pin coordinates and pin number definition.
37. Figure 6.37 LP Wizard professional library tool.
38. Figure 6.38 Create a new part in Part Editor.
39. Figure 6.39 Pin Mapping window.
40. Figure 6.40 Import symbol and cell.
41. Figure 6.41 Symbol and cell have been mapped.
42. Figure 6.42 Symbol/Cell Preview window.
43. Figure 6.43 BGA Symbol/Cell Preview window.
44. Figure 6.44 Create part with no corresponding cell.
45. Figure 6.45 Cell inherits the pin numbers defined in symbol automatically.
Chapter 7: Schematic Input
1. Figure 7.1 Keyin netlist format.
2. Figure 7.2 Create project with Job Management Wizard.
3. Figure 7.3 Assign central library and netlist for the new project.
4. Figure 7.4 Specify layout design path and templates, complete project creation.
5. Figure 7.5 Extra licenses support extra functionality.
6. Figure 7.6 Bold font indicates that FLIPCHIP_DESIGN is the active project.
7. Figure 7.7 DxDesigner opens the active project automatically on startup.
8. Figure 7.8 Project tab in Navigator.
9. Figure 7.9 Simulation tab in Navigator.
10. Figure 7.10 RF Groups tab in Navigator.
11. Figure 7.11 DxDataBook window.
12. Figure 7.12 Add nets and net names in schematic.
13. Figure 7.13 ICT Viewer.
14. Figure 7.14 eExp View in schematic.
15. Figure 7.15 Selection Filter in DxDesigner.
16. Figure 7.16 Adding properties to components and nets.
17. Figure 7.17 Create a new project in DxDesigner.
18. Figure 7.18 Create new board and corresponding schematic, then rename.
19. Figure 7.19 Search for and place components using filter function.
20. Figure 7.20 Automatically add nets and net names.
21. Figure 7.21 Draw function block and add net connections in schematic.
22. Figure 7.22 Special components definition and use.
23. Figure 7.23 Array copy circuit diagram.
24. Figure 7.24 DRC (Schematic) Settings window.
25. Figure 7.25 Schematic DRC Rules window.
26. Figure 7.26 Schematic DRC report.
27. Figure 7.27 CES interface.
28. Figure 7.28 Packager window.
29. Figure 7.29 Operation items.
30. Figure 7.30 Optimization options.
31. Figure 7.31 Other options.
32. Figure 7.32 PDB Extraction Options.
33. Figure 7.33 Library extraction options in Expedition.
34. Figure 7.34 The report information after packaging has finished successfully.
35. Figure 7.35 Output Excel format partlist.
36. Figure 7.36 Columns and Advanced tabs of Part Lister.
37. Figure 7.37 Chinese font mapping.
38. Figure 7.38 Input a variety of Chinese fonts in schematic.
39. Figure 7.39 Display effect comparison before and after font mapping.
40. Figure 7.40 Select layout template and PCB board directory.
41. Figure 7.41 Create PCB directory.
42. Figure 7.42 Back annotation has been disabled for current project.
43. Figure 7.43 DxDataBook interface.
44. Figure 7.44 Open the Central_Lib.dbc file.
45. Figure 7.45 Select CIS.mdb database file.
46. Figure 7.46 DxDataBook component list.
47. Figure 7.47 A component in the schematic and its properties.
48. Figure 7.48 List components of manufacturer TI.
49. Figure 7.49 Open the device manual via the dynamic link.
50. Figure 7.50 Transistor partition of DxDataBook.
51. Figure 7.51 Connector partition of DxDataBook.
52. Figure 7.52 Delete the property value artificially.
53. Figure 7.53 Component attribute status display.
54. Figure 7.54 Update the component properties with DxDataBook.
55. Figure 7.55 Component properties have been updated in the schematic.
Chapter 8: Multi-board Project Management and Concurrent Schematic Design
1. Figure 8.1 Chip, SiP and PCB relationship and the signal pathway.
2. Figure 8.2 One project manages multiple boards.
3. Figure 8.3 Multi-board project schematic design.
4. Figure 8.4 Three boards are placed under different paths.
5. Figure 8.5 SiP1, SiP2 and PCB_board; each has its own independent design environment.
6. Figure 8.6 Traditional circuit design separately and then copy together.
7. Figure 8.7 The operation of concurrent schematic design.
8. Figure 8.8 Enable concurrent schematic design and set the server name.
9. Figure 8.9 Enable edit mode for opened sheets option checked and unchecked comparison.
10. Figure 8.10 When a designer edits the sheet, other participants can see in real-time.
11. Figure 8.11 For other designers, the sheet is read-only.
12. Figure 8.12 The designer who first clicks the “Click to Edit” button has write permission to the sheet.
Chapter 9: Layout Creation and Setting
1. Figure 9.1 2+4+2 HDI layer stackup.
2. Figure 9.2 Start Layout Template Editor.
3. Figure 9.3 New Layout Template.
4. Figure 9.4 Copy template and rename.
5. Figure 9.5 Start the template Setup Parameters window.
6. Figure 9.6 Remap layers.
7. Figure 9.7 Via definition of layout template.
8. Figure 9.8 Four types of drill symbol.
9. Figure 9.9 Create drill hole and specify the corresponding drill symbol.
10. Figure 9.10 Create pads.
11. Figure 9.11 Create padstack for via.
12. Figure 9.12 The definition of layer stackup 2 + 4 + 2.
13. Figure 9.13 Layer Stackup setup.
14. Figure 9.14 Dimension Parameters window.
15. Figure 9.15 Copy route border and change the size.
16. Figure 9.16 The three key elements of the layout template.
17. Figure 9.17 Create new project.
18. Figure 9.18 Layout template selection and directory settings.
19. Figure 9.19 Forward Annotation prompt and indication.
20. Figure 9.20 Prompt window indicates forward annotation successful or shows warning.
21. Figure 9.21 Check ForwardAnnotation.txt file.
22. Figure 9.22 Expedition interface.
23. Figure 9.23 Expedition license control.
24. Figure 9.24 License control window before entering Expedition.
25. Figure 9.25 The functions of the mouse in Expedition.
26. Figure 9.26 Right mouse button strokes.
27. Figure 9.27 Switch from right-mouse-button stroke to middle-mouse-button stroke.
28. Figure 9.28 Comparison of components in selected state and unselected state.
29. Figure 9.29 Find and select components with the Find command.
30. Figure 9.30 Select trace or net.
31. Figure 9.31 Find and select net with Find command.
32. Figure 9.32 Select and edit plane shape and component outline in draw mode.
33. Figure 9.33 Draw various kinds of graphics in draw mode.
34. Figure 9.34 Layer visibility and color setting.
35. Figure 9.35 Display color and pattern setting window.
36. Figure 9.36 Display Control item grouping.
37. Figure 9.37 Save and delete display scheme.
38. Figure 9.38 Layer tab, General tab and Part tab of Display Control.
39. Figure 9.39 Use Selected only option to view net topology (with shadow mode shown on the right).
40. Figure 9.40 Display Tuning Meter.
41. Figure 9.41 Net tab, Hazard tab and Groups tab of Display Control.
42. Figure 9.42 Place tab, Route tab, Grids tab and Common Settings.
43. Figure 9.43 When interactive DRC is closed, the system shows a “DRC Off” warning.
44. Figure 9.44 Interactive DRC re-open prompt window.
45. Figure 9.45 Edit control window operation introduction.
46. Figure 9.46 Route tab Dialogs option expanded step by step.
47. Figure 9.47 Net Filter method.
48. Figure 9.48 Allow via under pad settings.
49. Figure 9.49 Trace & via edit behavior option.
50. Figure 9.50 General options.
51. Figure 9.51 Plow options.
52. Figure 9.52 Vias & fanouts.
53. Figure 9.53 Grids tab.
54. Figure 9.54 Place Parts and Cells window.
55. Figure 9.55 Cross probe of schematic and layout.
56. Figure 9.56 Components and net connections after placement.
57. Figure 9.57 Net connections after automatic optimization.
58. Figure 9.58 Create eDxD and eExp data during forward annotation.
59. Figure 9.59 View schematic in layout environment.
60. Figure 9.60 Chinese characters input in layout.
61. Figure 9.61 DXF file import.
62. Figure 9.62 Chinese characters imported from DXF can be edited in layout.
Chapter 10: Constraint Rules Management
1. Figure 10.1 The flow of constraint rules transmission.
2. Figure 10.2 The designer can start CES from schematic or layout.
3. Figure 10.3 CES interface.
4. Figure 10.4 Create a new custom scheme.
5. Figure 10.5 Modify the rules in the custom scheme.
6. Figure 10.6 Apply myarea scheme in Rule Area.
7. Figure 10.7 Stackup Editor in CES.
8. Figure 10.8 The layer stackup information copied to Word.
9. Figure 10.9 Create new net class.
10. Figure 10.10 Assign nets to net class.
11. Figure 10.11 Define the trace width rules for net class Suny_New.
12. Figure 10.12 Define the net class via.
13. Figure 10.13 Create a new clearance rule.
14. Figure 10.14 Clearance rules setup.
15. Figure 10.15 Set up clearance rules and adjusting column width.
16. Figure 10.16 Reset column widths and row heights.
17. Figure 10.17 General clearance rules definition.
18. Figure 10.18 Net class to net class clearance rules definition.
19. Figure 10.19 Create new constraint class and assign nets to the constraint class.
20. Figure 10.20 Constraint classes classification.
21. Figure 10.21 Delays and Lengths.
22. Figure 10.22 Differential Pair Properties.
23. Figure 10.23 I/O standard.
24. Figure 10.24 Net properties.
25. Figure 10.25 Overshoot/Ringback.
26. Figure 10.26 Simulated delays.
27. Figure 10.27 Template group.
28. Figure 10.28 Start Edit Constraint Groups.
29. Figure 10.29 Create new constraint group and assign constraints to it.
30. Figure 10.30 Actual routing length compared with the length set in CES.
Chapter 11: Wire Bond Design
1. Figure 11.1 Connect chip and substrate through wire bond.
2. Figure 11.2 Expedition supports the most complex wire bonding design.

Chapter 12: Cavity and Chip Stack Design

Figure 12.1 Open multistep cavity.

Figure 12.2 The eight-layer stackup.

Figure 12.3 The eight-layer stackup with 1–3 layer cavity profile.

Figure 12.4 The eight-layer stackup with multistep cavity profile.

Figure 12.5 The eight-layer stackup with embedded cavity profile.

Figure 12.6 Cavity properties definition.

Figure 12.7 1–2 layer cavity structure.

Figure 12.8 Properties setup for different cavities.

Figure 12.9 Multistep cavity and single-step cavity comparison.

Figure 12.10 Place component into cavity.

Figure 12.11 Place component crossing over the cavity.

Figure 12.12 Place components into cavity.

Figure 12.13 Bond pad cannot be placed across the cavity boundary.

Figure 12.14 Bond wire profile will adjust with bond pad move.

Figure 12.15 Two-sided multistep cavity and chip-bonding profile of a real project.

Figure 12.16 Draw an open-type cavity in the substrate.

Figure 12.17 Place the chip into the open cavity.

Figure 12.18 Change the start layer of the cavity to layer 4.

Figure 12.19 Chip was embedded in the inner layer of the substrate.

Figure 12.20 The position of the embedded chip and trace in each layer.

Figure 12.21 Real photo of chip stack.

Figure 12.22 Chips, interposer and bond wires in chip stack (Expedition 3D Viewer).

Figure 12.23 Chip stack pyramid and chip stack cantilever.

Figure 12.24 Interposer creation windows.

Figure 12.25 Chip stack configuration window.

Figure 12.26 Chip stack operations.

Figure 12.27 Chips in stack with different rotation angles.

Figure 12.28 Stacking chips side by side.

Figure 12.29 Set chips stacked side by side in the same layer.

Figure 12.30 Adjust relative position of chips in stack.

Figure 12.31 Chip stack setup complete.

Figure 12.32 Chip stack automatic bonding setup.

Figure 12.33 The effect of manual bonding of chip stack.

Figure 12.34 Chip stack is placed in the cavity for bonding.

Figure 12.35 A real project with multistep cavity bonding.

Figure 12.36 A real project with mixed design technologies.

Chapter 13: Flip Chip and RDL Design

Figure 13.1 Flip chip diagram.

Figure 13.2 RDL diagram (chip-top view).

Figure 13.3 RDL diagram (side view).

Figure 13.4 Bare die cell, RDL cell and BGA cell positions on substrate (side view).

Figure 13.5 Bare die cell, RDL cell and BGA cell locations on substrate (3D view).

Figure 13.6 RDL padstack creation and parameters setup window.

Figure 13.7 Bare die cell and RDL cell properties setup.

Figure 13.8 The bare die cell and RDL cell.

Figure 13.9 RDL schematic design.

Figure 13.10 RDL layer stackup setting.

Figure 13.11 Bare die cell and RDL cell placement.

Figure 13.12 Net connections before auto-optimization.

Figure 13.13 Set part pins swappable.

Figure 13.14 Automatic net optimization interface.

Figure 13.15 Manually swap pins of RDL cell to optimize the net connection.

Figure 13.16 Automatically optimized net connection and its manual counterpart.

Figure 13.17 Two methods for back annotation.

Figure 13.18 The schematic updated after back annotation.

Figure 13.19 Disable or enable the 45° route function.

Figure 13.20 The results of the two types of routing.

Figure 13.21 FC_PACKAGE schematic design.

Figure 13.22 FC_PACKAGE substrate layer stackup setting.

Figure 13.23 FC_PACKAGE via settings.

Figure 13.24 FC_PACKAGE placement.

Figure 13.25 Design rules setup in CES.

Figure 13.26 Comparison of before and after auto-optimization.

Figure 13.27 Start Auto Route.

Figure 13.28 Auto route completion status.

Figure 13.29 2D view and 3D view after route completion.

Figure 13.30 Flip chip area trace and via in 3D view.

Figure 13.31 Trace and via 3D view in BGA area.

Figure 13.32 Add testing PCB_board to the same project.

Figure 13.33 Diagram for IC bare die→RDL→BGA package→PCB board.

Chapter 14: Route and Plane

Figure 14.1 The two route toolbar display modes.

Figure 14.2 Single plow.

Figure 14.3 Multi-plow.

Figure 14.4 Plow mode selection in Editor Control.

Figure 14.5 Forced plow.

Figure 14.6 Route plow.

Figure 14.7 Angle plow.

Figure 14.8 Fix and Lock tool bar.

Figure 14.9 Traces in states fix, semi-fix, unfix, lock and unlock displayed together.

Figure 14.10 Before and after a via is placed.

Figure 14.11 Layer pair and related route settings.

Figure 14.12 Using Display Control for layer switch.

Figure 14.13 Single-click selection and selection clicking start and end points.

Figure 14.14 Selection Filter window.

Figure 14.15 Component and net mapping in circuit copy.

Figure 14.16 Copy circuit and place to specified location.

Figure 14.17 There are no equivalent components and nets in the design.

Figure 14.18 Circuit copy realization (including substrate cavity).

Figure 14.19 Select pads then execute fan out.

Figure 14.20 Auto route dialog box.

Figure 14.21 The auto route options.

Figure 14.22 Nets included for auto route.

Figure 14.23 Set up diff pairs in the schematic.

Figure 14.24 Create and remove diff pairs in CES manually.

Figure 14.25 Set up diff pairs in CES automatically.

Figure 14.26 Finish automatic diff pair setup.

Figure 14.27 Completed diff pair routing.

Figure 14.28 Set up length rules in CES.

Figure 14.29 Tuning rules setup.

Figure 14.30 Tuning results with the Use arcs option selected and not selected.

Figure 14.31 Tuning effects with different setting combinations.

Figure 14.32 Automatic tune setup.

Figure 14.33 Serpentine tuning form and trombone tuning form.

Figure 14.34 Manual tune effect.

Figure 14.35 Import the actual tuning length.

Figure 14.36 Positive plane and negative plane.

Figure 14.37 Thermal definition in the Plane Classes and Parameters window.

Figure 14.38 Clearances/Discard/Negative tab.

Figure 14.39 Two different settings for the Negative plane fill distance beyond route border option.

Figure 14.40 Hatch Options tab.

Figure 14.41 Plane Assignments window.

Figure 14.42 Assign nets to plane layer.

Figure 14.43 Plane shape properties window.

Figure 14.44 Draw VDD plane shape.

Figure 14.45 Draw VEE plane shape.

Figure 14.46 Actual plane data.

Figure 14.47 Modify plane shape by adding or subtracting graphics.

Figure 14.48 Three types of vertex.

Figure 14.49 Comparison of VDD net before and after plane-shape editing.

Figure 14.50 Generate negative plane data.

Figure 14.51 Comparison before and after negative plane data generation.

Figure 14.52 Batch DRC check items for plane and discard options in Plane Classes and Parameters.

Chapter 15: Embedded Passives Design

Figure 15.1 Discrete devices embedded with closed cavity in Expedition.

Figure 15.2 Embedded resistors, capacitors and inductors in substrate.

Figure 15.3 Material/ Process Editor window in the central library.

Figure 15.4 Expedition supports multiple processes.

Figure 15.5 Common parameters definition for additive resistors.

Figure 15.6 Expedition supports four types of resistor shape.

Figure 15.7 Shape Specific definition window for additive resistor.

Figure 15.8 Common parameters definition window of subtractive resistor.

Figure 15.9 Shape Specific definition window of subtractive resistor.

Figure 15.10 Capacitor common parameters definition window.

Figure 15.11 Capacitor Interdigitated & Mezzanine parameter-setup window.

Figure 15.12 Interdigitated capacitor structure.

Figure 15.13 Mezzanine capacitor.

Figure 15.14 Capacitor Printed window.

Figure 15.15 Materials definition list.

Figure 15.16 Capacitor material parameters window.

Figure 15.17 Conductor material parameters window.

Figure 15.18 Insulator material properties window.

Figure 15.19 Resistor material properties window.

Figure 15.20 Nonlinear resistivity curve.

Figure 15.21 Nonlinear resistance curve.

Figure 15.22 Define resistor properties in Part Editor.

Figure 15.23 Define capacitor properties in Part Editor.

Figure 15.24 Enable Advanced Technology Pro (EP) license.

Figure 15.25 Resistor Planner interface.

Figure 15.26 Capacitor Planner interface.

Figure 15.27 Resistor Optimizer interface.

Figure 15.28 Define the layers allowed for embedded materials.

Figure 15.29 Put resistors for synthesizing to the right side of the window.

Figure 15.30 Return to Optimizer interface.

Figure 15.31 Resistors are synthesized and optimized.

Figure 15.32 Discrete resistors are automatically synthesized to planar resistors.

Figure 15.33 Toggle planar resistors to discrete resistors.

Figure 15.34 Capacitor Optimizer interface.

Figure 15.35 Capacitors are synthesized and optimized.

Figure 15.36 Discrete capacitors are automatically synthesized to planar capacitors.

Figure 15.37 Resistors and capacitors before synthesis.

Figure 15.38 Resistors and capacitors after synthesis.

Chapter 16: RF Circuit Design

Figure 16.1 The RF circuit design and simulation process in EE Flow.

Figure 16.2 Library configuration batch file content.

Figure 16.3 Parameterized RF shapes library path and current design central library path.

Figure 16.4 RF shapes imported to user central library.

Figure 16.5 Enable DxRFEngineer license.

Figure 16.6 RF tools in DxDesigner.

Figure 16.7 RF Connect status before and after connection.

Figure 16.8 RF Group interface and RF data generate and send menu.

Figure 16.9 Find corresponding RF symbol by clicking the DRC message.

Figure 16.10 RF Parameters window.

Figure 16.11 RF default-unit setting window.

Figure 16.12 RF Frequency Range Setup window.

Figure 16.13 RF Set up substrates window.

Figure 16.14 RF Substrates properties edit window.

Figure 16.15 Default substrates can't be deleted.

Figure 16.16 Select RF shapes in Symbol View.

Figure 16.17 Input RF symbols in DxDesigner and connect with nets.

Figure 16.18 The status lamps and prompt texts change before and after forward annotation.

Figure 16.19 Placing parameterized RF shapes in layout.

Figure 16.20 RF shapes layout.

Figure 16.21 Transfer RF parameters from RF symbol to RF cell.

Figure 16.22 RF parameters can be transferred between schematic and layout.

Figure 16.23 RF parameters are transferred from schematic to layout.

Figure 16.24 RF parameters are transferred from layout back to schematic.

Figure 16.25 RF toolkit.

Figure 16.26 Select from the menu Setup→RF.

Figure 16.27 Right-click menu to invoke RF tools.

Figure 16.28 RF soft-key functions when an RF unit is not selected.

Figure 16.29 RF soft-key functions when an RF unit is selected.

Figure 16.30 RF parameter two-way transfer between schematic and layout.

Figure 16.31 Segments and nodes of RF shapes.

Figure 16.32 Draw meander in layout.

Figure 16.33 Switch meander layer through via.

Figure 16.35 RF Library Shapes tab and RF Design tab.

Figure 16.36 Create custom RF shape.

Figure 16.37 Using RF via to connect different layers.

Figure 16.38 Interactive place via.

Figure 16.39 Stitch contour.

Figure 16.40 Stitch shape.

Figure 16.41 Radial place via.

Figure 16.42 Array place via.

Figure 16.43 RF group operations.

Figure 16.44 RF group display control.

Figure 16.45 RF parameter changes are reflected in RF shape change.

Figure 16.46 Edit RF shape clearance.

Figure 16.47 Define RF entry rules.

Figure 16.48 RF filter and Circuit Move and Copy filter.

Figure 16.49 Three tabs of RF Connect.

Figure 16.50 Mentor Design Kit installed in ADS.

Figure 16.51 Start Mentor Server connection in ADS.

Figure 16.52 Start RF Connect in Expedition.

Figure 16.53 Transfer layout design data to ADS.

Figure 16.54 Transmit RF layout data from Expedition to ADS.

Figure 16.55 Transfer schematic RF data to ADS.

Figure 16.56 Transmit Schematic RF data from DxDesigner to ADS.

Figure 16.57 RF parameters in DxDesigner are transferred to ADS.

Chapter 17: Concurrent Layout Design

Figure 17.1 Multiplayer concurrent layout design sketch map.

Figure 17.2 Data transmission in Xtreme concurrent design.

Figure 17.3 Independent server mode.

Figure 17.4 The client folder-sharing mode.

Figure 17.5 Start Xtreme Design Session.

Figure 17.6 XDS starts normally.

Figure 17.7 Each designer opens the same design with Xtreme Design Client (XDC).

Figure 17.8 The participating designers are shown in the XDS window.

Figure 17.9 Different designers' design windows in concurrent design.

Figure 17.10 The edit operation shown in the interface of designer A.

Figure 17.11 Notification to the last designer exiting the design session.

Figure 17.12 SingleUserMode value should be auto or no.

Chapter 18: 3D Real-time DRC

Figure 18.1 Wire Model Editor and 3D Viewer.

Figure 18.2 Bond wire model in Wire Model Editor.

Figure 18.3 The window shows blank when elements not related to bond wire are selected.

Figure 18.4 The display state when the bond wire is reselected.

Figure 18.5 The adjustment result of bond wire displays in real-time.

Figure 18.6 Alert window pops up automatically when 3D DRC rules are violated.

Figure 18.7 Display filters and eye position options.

Figure 18.8 Display effects of translucent and opaque modes.

Figure 18.9 The display interface of 3D Viewer.

Figure 18.10 3 Display control tabs in 3D Viewer.

Figure 18.11 Substrate 3D view when plane data is opened and closed.

Figure 18.12 Transparent and solid display modes.

Figure 18.13 3D display of trace, plane data and via in substrate.

Figure 18.14 3D display after the completion of substrate production.

Figure 18.15 3D display after chip assembly and die attach.

Figure 18.16 3D display of finished wire bonding.

Figure 18.17 3D display after molding.

Figure 18.18 3D display after bumping.

Figure 18.19 View SiP product from three directions in 3D Viewer.

Figure 18.20 SiP mold designed in Blender software.

Figure 18.21 SiP bumps designed in Blender software.

Figure 18.22 Import mold and bumps in 3D Viewer.

Figure 18.23 Imported mold and bump display in 3D Viewer.

Figure 18.24 3D Cell Import window.

Figure 18.25 Comparison of before and after import of mechanical 3D cell.

Figure 18.26 Import mechanical shell data.

Figure 18.27 After mechanical shell import.

Figure 18.28 Conflict occurs between component and shell.

Figure 18.29 Conflict occurs between components.

Chapter 19: Design Review

Figure 19.1 Online DRC turned off and the notification window and box.

Figure 19.2 The two tabs of the Batch DRC interface.

Figure 19.3 Check entire design.

Figure 19.4 Check selected nets only and check all nets of the design.

Figure 19.5 General and element to element rules.

Figure 19.6 Element to Element rules window.

Figure 19.7 Restore default clearance rules from CES.

Figure 19.8 Pad to pad checks option.

Figure 19.9 Save DRC scheme.

Figure 19.10 Batch DRC prompt interface (the left showing hazards found, the right no hazards).

Figure 19.11 Partial content of Drc.txt file.

Figure 19.12 Review Hazard window.

Figure 19.13 Fit view for the hanger hazard.

Figure 19.14 Partial contents of VerifyLocal2CentralLibrary.txt file.

Figure 19.15 Local library and central library data synchronization.

Chapter 20: Manufacturing Data Output

Figure 20.1 Drill Options tab.

Figure 20.2 Drill Chart Options tab.

Figure 20.3 Drill Symbols tab.

Figure 20.4 Drill files for layer stackup 3+4+3.

Figure 20.5 Drill drawing and drill chart.

Figure 20.6 Import drill data for review (including drill symbols).

Figure 20.7 Gerber machine format setting.

Figure 20.8 Gerber Output tab.

Figure 20.9 Gerber file content selection.

Figure 20.10 Output bond wire graphics (partial).

Figure 20.11 Import and review Gerber data.

Figure 20.12 Output Generic AIS file.

Figure 20.13 The vb_ais.txt file format.

Figure 20.14 Wirebond report file was created.

Figure 20.15 Bond wire report file format.

Figure 20.16 DXF Export window options.

Figure 20.17 Design Status file format.

Figure 20.18 BOM export interface.

Figure 20.19 BOM file (includes two kinds of classification rules).

Chapter 21: SiP Simulation Technology

Figure 21.1 From Expedition export design data to simulation tools.

Figure 21.2 HyperLynx SI simulation screenshots.

Figure 21.3 Flip chip layout design in Expedition.

Figure 21.4 Flip chip design is imported in HyperLynx.

Figure 21.5 Select key net.

Figure 21.6 The key signal GCK0 net is selected.

Figure 21.7 Specify simulation model.

Figure 21.8 Specify the input and output buffers of the simulation model.

Figure 21.9 Digital oscilloscope displays simulation results.

Figure 21.10 Terminator Wizard.

Figure 21.11 The simulation results after termination.

Figure 21.12 Comparison of original signal and terminated signal.

Figure 21.13 The chip model after package.

Figure 21.14 Extract S-Parameter model.

Figure 21.15 Assign S-parameter model.

Figure 21.16 Connect driver and receiver through S-Parameter.

Figure 21.17 The simulation result with S-Parameter model.

Figure 21.18 HyperLynx PI simulation screenshots.

Figure 21.19 The results of DC drop analysis.

Figure 21.20 The impedance curve of the plane layer with different capacitor distributions.

Figure 21.21 Plane-layer noise analysis.

Figure 21.22 Transfer design data to HyperLynx PI.

Figure 21.23 DC drop analysis interface.

Figure 21.24 Model assignment window of PI analysis.

Figure 21.25 Assign VRM Model window.

Figure 21.26 Assign DC Sink model.

Figure 21.27 DC voltage drop 3D graphics display window.

Figure 21.28 DC drop report window.

Figure 21.29 3D graphic of current density.

Figure 21.30 HyperLynx Thermal screenshot.

Figure 21.31 Transfer data from Expedition to HyperLynx Thermal.

Figure 21.32 Environment condition definition.

Figure 21.33 Component property setting.

Figure 21.34 Substrate board property definition.

Figure 21.35 The VFM value when VCC/GND copper-layer thickness set to 0.5 Oz.

Figure 21.36 The highest substrate temperature is 154°C, when VFM=0.0756.

Figure 21.37 The maximum temperature gradient of the substrate is 10.5°C/inch when VFM=0.0756.

Figure 21.38 The VFM value when VCC/GND copper-layer thickness set to 1 Oz.

Figure 21.39 The highest substrate temperature is 151 °C when VFM=0.1076.

Figure 21.40 The temperature gradient is 8.3 °C/inch when VFM=0.1076.

Figure 21.41 Change power-scaling factor to 0.25.

Figure 21.42 The highest temperature is 122 °C when run with 25% power consumption.

Figure 21.43 The maximum temperature gradient is 1.3 °C/inch when run with 25% power consumption.

Figure 21.44 Boundary Condition Definition.

Figure 21.45 Substrate temperature after adding boundary condition.

Figure 21.46 Temperature gradient after adding boundary condition.

Figure 21.47 HyperLynx DRC verification process.

Figure 21.48 Transfer data from Expedition to HyperLynx DRC.

Figure 21.49 DRC rules in HyperLynx DRC.

Figure 21.50 The color indicates DRC checking fail or pass.

Figure 21.51 Violation display.

Figure 21.52 The violation net is highlighted.

Figure 21.53 HyperLynx DRC cross probe with Expedition.

Figure 21.54 Enable HyperLynx Analog license in DxDesigner.

Figure 21.55 HyperLynx Analog simulation interface.

Figure 21.56 The waveforms of HyperLynx Analog simulation.

List of Tables

Chapter 4: New Package Technologies

Table 4.1 Via-first and via-last technology comparison.

Table 4.2 TSV hot technologies.

Chapter 9: Layout Creation and Setting

Table 9.1 Stroke actions and corresponding operands.

Chapter 14: Route and Plane

Table 14.1 Detailed tuning rules settings.

Chapter 16: RF Circuit Design

Table 16.1 RF units.

Table 16.2 The default substrate layers.

Table 16.3 RF Shape toolbar description.

Table 16.4 RF Node and Segment toolbar description.

Table 16.5 RF General toolbar description.

Table 16.6 RF soft-key and sub-soft-key function descriptions.

Table 16.7 Meander properties description.

Chapter 17: Concurrent Layout Design

Table 17.1 Xtreme concurrent design configuration table.

Chapter 20: Manufacturing Data Output

Table 20.1 Gerber file format options description.

Table 20.2 Output Gerber file configuration.

SiP System-in-Package Design and Simulation

Mentor EE Flow Advanced Design Guide

Suny Li (Li Yang)

SiP/PCB Technical Specialist
Beijing, China

This edition first published 2017 by John Wiley & Sons Singapore Pte. Ltd under exclusive license granted by Publishing House of Electronics Industry for all media and languages (excluding simplified and traditional Chinese) throughout the world (excluding Mainland China), and with non-exclusive license for electronic versions in Mainland China.

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Library of Congress Cataloging-in-Publication Data

Names: Li (Li Yang), Suny, 1974- author.

Title: SiP system-in-package design and simulation : Mentor EE Flow advanced design guide / Suny Li (Li Yang).

Description: Singapore ; Hoboken, NJ : John Wiley & Sons, 2017. | Includes bibliographical references and index.

Identifiers: LCCN 2017007232 (print) | LCCN 2017011202 (ebook) | ISBN 9781119045939 (cloth) | ISBN 9781119046011 (Adobe PDF) | ISBN 9781119046004 (ePub)

Subjects: LCSH: Integrated circuits--Design and construction. | Multichip modules (Microelectronics)-Design and construction.

Classification: LCC TK7874 .L437 2017 (print) | LCC TK7874 (ebook) | DDC 621.3815-dc23

LC record available at https://lccn.loc.gov/2017007232

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Cover Images: (Background) © KTSDESIGN/Gettyimages; (Gold Chip) Courtesy of the author

About the Author

Mr. Suny Li (Li Yang) is an SiP/PCB Technical Specialist in China; he now works in AcconSys Technology Co., Ltd, (a Mentor Authorized Distributor for China).

Suny has guided and consulted on dozens of SiP projects in China, accumulating plentiful experience in SiP design and simulation.

Suny has 10 years' experience in and knowledge of Application Engineer for Mentor especially in SiP/PCB design and simulation.

Before this, Suny worked in the Chinese Academy of Science and SIEMENS for several years. He has more than seven years' experience in hardware design (HW system design, PCB layout, high-speed signal integrity, power integrity, EMI, etc.).

In the course of his work, Suny has published papers and acquired four patents, and he continues with this work.

Suny is a senior member of the Chinese Institute of Electronics (CIE) and a member of the IEEE.

Suny graduated from Beijing University of Aeronautics & Astronautics (BUAA) in 2000, receiving Master's and Bachelor's degrees in Science and Technology of Aeronautics & Astronautics.