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Library of Congress Cataloging-in-Publication Data

Names: Chu, Pong P., 1959-author.
Title: FPGA prototyping by systemVERILOG examples. Xilinx MicroBlaze MCS SoC Edition
/ by Pong P. Chu, Cleveland State University.
Description: Hoboken, NJ, USA : Wiley, 2018. | Includes bibliographical references and index. |
Identifiers: LCCN 2018005487 (print) | LCCN 2018006519 (ebook) | ISBN
9781119282693 (pdf) | ISBN 9781119282709 (epub) | ISBN 9781119282662
(cloth)
Subjects: LCSH: Field programmable gate arrays--Design and construction. |
Prototypes, Engineering. | VHDL (Computer hardware description language)
Classification: LCC TK7895.G36 (ebook) | LCC TK7895.G36 C4835 2018 (print) |
DDC 621.39/5--dc23
LC record available at https://lccn.loc.gov/2018005487

Cover image: Courtesy of Pong P. Chu
Cover design by Wiley

Contents

Preface

Focus and audience
Changes for the MicroBlaze MCS SoC Edition

Acknowledgments

PART I: BASIC DIGITAL CIRCUITS DEVELOPMENT

CHAPTER 1: GATE-LEVEL COMBINATIONAL CIRCUIT
1. 1.1 INTRODUCTION
2. 1.2 GENERAL DESCRIPTION
3. 1.3 BASIC LEXICAL ELEMENTS AND DATA TYPES
4. 1.4 PROGRAM SKELETON
5. 1.5 STRUCTURAL DESCRIPTION
6. 1.6 TOP-LEVEL SIGNAL MAPPING
7. 1.7 TESTBENCH
8. 1.8 BIBLIOGRAPHIC NOTES
9. 1.9 SUGGESTED EXPERIMENTS
Chapter 2: OVERVIEW OF FPGA AND EDA SOFTWARE
1. 2.1 FPGA
2. 2.2 OVERVIEW OF THE DIGILENT NEXYS 4 DDR BOARD
3. 2.3 DEVELOPMENT FLOW
4. 2.4 XILINX VIVADO DESIGN SUITE
5. 2.5 BIBLIOGRAPHIC NOTES
6. 2.6 SUGGESTED EXPERIMENTS
CHAPTER 3: RT-LEVEL COMBINATIONAL CIRCUIT
1. 3.1 OPERATORS
2. 3.2 ALWAYS BLOCK FOR A COMBINATIONAL CIRCUIT
3. 3.3 CODING GUIDELINES
4. 3.4 IF STATEMENT
5. 3.5 CASE STATEMENT
6. 3.6 ROUTING STRUCTURE OF CONDITIONAL CONTROL CONSTRUCTS
7. 3.7 ADDITIONAL CODING GUIDELINES FOR AN ALWAYS BLOCK
8. 3.8 PARAMETER AND CONSTANT
9. 3.9 REPLICATED STRUCTURE
10. 3.10 DESIGN EXAMPLES
11. 3.11 BIBLIOGRAPHIC NOTES
12. 3.12 SUGGESTED EXPERIMENTS
CHAPTER 4: REGULAR SEQUENTIAL CIRCUIT
1. 4.1 INTRODUCTION
2. 4.2 HDL CODE OF THE FF AND REGISTER
3. 4.3 SIMPLE DESIGN EXAMPLES
4. 4.4 TESTBENCH FOR SEQUENTIAL CIRCUITS
5. 4.5 CASE STUDY
6. 4.6 TIMING AND CLOCKING
7. 4.7 BIBLIOGRAPHIC NOTES
8. 4.8 SUGGESTED EXPERIMENTS
CHAPTER 5: FSM
1. 5.1 INTRODUCTION
2. 5.2 FSM CODE DEVELOPMENT
3. 5.3 DESIGN EXAMPLES
4. 5.4 BIBLIOGRAPHIC NOTES
5. 5.5 SUGGESTED EXPERIMENTS
CHAPTER 6: FSMD
1. 6.1 INTRODUCTION
2. 6.2 CODE DEVELOPMENT OF AN FSMD
3. 6.3 DESIGN EXAMPLES
4. 6.4 BIBLIOGRAPHIC NOTES
5. 6.5 SUGGESTED EXPERIMENTS
CHAPTER 7: RAM AND BUFFER OF FPGA
1. 7.1 EMBEDDED MEMORY OF FPGA DEVICE
2. 7.2 GENERAL DESCRIPTION FOR A RAM-LIKE COMPONENT
3. 7.3 FIFO BUFFER
4. 7.4 HDL TEMPLATES FOR MEMORY INFERENCE
5. 7.5 OVERVIEW OF MEMORY CONTROLLER
6. 7.6 BIBLIOGRAPHIC NOTES
7. 7.7 SUGGESTED EXPERIMENTS
CHAPTER 8: SELECTED TOPICS OF SYSTEMVERILOG
1. 8.1 TIMING MODEL
2. 8.2 CODING GUIDELINES REVISITED
3. 8.3 ALTERNATIVE CODING STYLE
4. 8.4 DATA TYPES
5. 8.5 USE OF THE SIGNED DATA TYPE
6. 8.6 BIBLIOGRAPHIC NOTES
7. 8.7 SUGGESTED EXPERIMENTS

PART II: EMBEDDED SOC I: VANILLA FPRO SYSTEM

CHAPTER 9: OVERVIEW OF EMBEDDED SOC SYSTEMS
1. 9.1 EMBEDDED SOC
2. 9.2 DEVELOPMENT FLOW OF THE EMBEDDED SOC
3. 9.3 FPRO SOC PLATFORM
4. 9.4 ADAPTATION ON THE DIGILENT NEXYS 4 DDR BOARD
5. 9.5 PORTABILITY
6. 9.6 ORGANIZATION
7. 9.7 BIBLIOGRAPHIC NOTES
CHAPTER 10: BARE METAL SYSTEM SOFTWARE DEVELOPMENT
1. 10.1 BARE METAL SYSTEM DEVELOPMENT OVERVIEW
2. 10.2 MEMORY-MAPPED I/O
3. 10.3 DIRECT I/O REGISTER ACCESS
4. 10.4 ROBUST I/O REGISTER ACCESS
5. 10.5 TECHNIQUES FOR LOW-LEVEL I/O OPERATIONS
6. 10.6 DEVICE DRIVERS
7. 10.7 FPRO UTILITY ROUTINES AND DIRECTORY STRUCTURE
8. 10.8 TEST PROGRAM
9. 10.9 BIBLIOGRAPHIC NOTES
10. 10.10 SUGGESTED EXPERIMENTS
CHAPTER 11: FPRO BUS PROTOCOL AND MMIO SLOT SPECIFICATION
1. 11.1 FPRO BUS
2. 11.2 INTERFACE WITH THE BUS
3. 11.3 MMIO I/O CORE
4. 11.4 TIMER CORE DEVELOPMENT
5. 11.5 MMIO CONTROLLER
6. 11.6 MCS I/O BUS AND BRIDGE
7. 11.7 VANILLA FPRO SYSTEM CONSTRUCTION
8. 11.8 BIBLIOGRAPHIC NOTES
9. 11.9 SUGGESTED EXPERIMENTS
CHAPTER 12: UART CORE
1. 12.1 INTRODUCTION
2. 12.2 UART CONSTRUCTION
3. 12.3 UART CORE DEVELOPMENT
4. 12.4 UART DRIVER
5. 12.5 ADDITIONAL PROJECT IDEAS
6. 12.6 BIBLIOGRAPHIC NOTES
7. 12.7 SUGGESTED EXPERIMENTS

PART III: EMBEDDED SOC II: BASIC I/O CORES

CHAPTER 13: XILINX XADC CORE
1. 13.1 OVERVIEW OF XADC
2. 13.2 XADC CORE DEVELOPMENT
3. 13.3 XADC CORE DEVICE DRIVER
4. 13.4 SAMPLER FPRO SYSTEM
5. 13.5 ADDITIONAL PROJECT IDEAS
6. 13.6 BIBLIOGRAPHIC NOTES
7. 13.7 SUGGESTED EXPERIMENTS
CHAPTER 14: PULSE WIDTH MODULATION CORE
1. 14.1 INTRODUCTION
2. 14.2 PWM DESIGN
3. 14.3 PWM CORE DEVELOPMENT
4. 14.4 PWM DRIVER
5. 14.5 TESTING
6. 14.6 PROJECT IDEAS
7. 14.7 SUGGESTED EXPERIMENTS
CHAPTER 15: DEBOUNCING CORE AND LED-MUX CORE
1. 15.1 DEBOUNCING CORE
2. 15.2 LED-MUX CORE
3. 15.3 PROJECT IDEAS
4. 15.4 SUGGESTED EXPERIMENTS
CHAPTER 16: SPI CORE
1. 16.1 OVERVIEW
2. 16.2 SPI CONTROLLER
3. 16.3 SPI CORE DEVELOPMENT
4. 16.4 SPI DRIVER
5. 16.5 TEST
6. 16.6 PROJECT IDEAS
7. 16.7 BIBLIOGRAPHIC NOTES
8. 16.8 SUGGESTED EXPERIMENTS
CHAPTER 17: I²C CORE
1. 17.1 OVERVIEW
2. 17.2 I²C CONTROLLER
3. 17.3 I²C CORE DEVELOPMENT
4. 17.4 I²C DRIVER
5. 17.5 TEST
6. 17.6 PROJECT IDEA
7. 17.7 BIBLIOGRAPHIC NOTES
8. 17.8 SUGGESTED EXPERIMENTS
CHAPTER 18: PS2 CORE
1. 18.1 INTRODUCTION
2. 18.2 PS2 CONTROLLER
3. 18.3 PS2 CORE DEVELOPMENT
4. 18.4 PS2 DRIVER
5. 18.5 TEST
6. 18.6 BIBLIOGRAPHIC NOTES
7. 18.7 SUGGESTED EXPERIMENTS
CHAPTER 19: SOUND I: DDFS CORE
1. 19.1 INTRODUCTION
2. 19.2 DESIGN AND IMPLEMENTATION
3. 19.3 FIXED-POINT ARITHMETIC
4. 19.4 DDFS CONSTRUCTION
5. 19.5 DAC (DIGITAL-TO-ANALOG CONVERTER)
6. 19.6 DDFS CORE DEVELOPMENT
7. 19.7 DDFS DRIVER
8. 19.8 TEST
9. 19.9 BIBLIOGRAPHIC NOTES
10. 19.10 SUGGESTED EXPERIMENTS
CHAPTER 20: SOUND II: ADSR CORE
1. 20.1 INTRODUCTION
2. 20.2 ADSR ENVELOPE GENERATOR
3. 20.3 ADSR CORE DEVELOPMENT
4. 20.4 ADSR DRIVER
5. 20.5 TEST
6. 20.6 PROJECT IDEA
7. 20.7 BIBLIOGRAPHIC NOTES
8. 20.8 SUGGESTED EXPERIMENTS

PART IV: EMBEDDED SOC III: VIDEO CORES

CHAPTER 21: INTRODUCTION TO THE VIDEO SYSTEM
1. 21.1 INTRODUCTION TO A VIDEO DISPLAY
2. 21.2 STREAM INTERFACE
3. 21.3 VGA SYNCHRONIZATION
4. 21.4 BAR TEST-PATTERN GENERATOR
5. 21.5 COLOR-TO-GRAYSCALE CONVERSION CIRCUIT
6. 21.6 DEMO VIDEO SYSTEM
7. 21.7 ADVANCED VIDEO STANDARDS
8. 21.8 BIBLIOGRAPHIC NOTES
9. 21.9 SUGGESTED EXPERIMENTS
CHAPTER 22: FPRO VIDEO SUBSYSTEM
1. 22.1 ORGANIZATION OF THE VIDEO SUBSYSTEM
2. 22.2 FPRO VIDEO IP CORE
3. 22.3 EXAMPLE VIDEO CORES
4. 22.4 FPRO VIDEO SYNCHRONIZATION CORE
5. 22.5 DAISY VIDEO SUBSYSTEM
6. 22.6 VANILLA DAISY FPRO SYSTEM
7. 22.7 VIDEO DRIVER AND TEST PROGRAM
8. 22.8 BIBLIOGRAPHIC NOTES
9. 22.9 SUGGESTED EXPERIMENTS
CHAPTER 23: SPRITE CORE
1. 23.1 INTRODUCTION
2. 23.2 BASIC DESIGN
3. 23.3 MOUSE POINTER CORE
4. 23.4 “GHOST” CHARACTER CORE
5. 23.5 SPRITE CORE DRIVER AND TEST PROGRAM
6. 23.6 BIBLIOGRAPHIC NOTES
7. 23.7 SUGGESTED EXPERIMENTS
CHAPTER 24: ON-SCREEN-DISPLAY CORE
1. 24.1 INTRODUCTION TO TILE GRAPHICS
2. 24.2 BASIC OSD DESIGN
3. 24.3 OSD CORE
4. 24.4 OSD CORE DRIVER AND TEST PROGRAM
5. 24.5 BIBLIOGRAPHIC NOTES
6. 24.6 SUGGESTED EXPERIMENTS
CHAPTER 25: VGA FRAME BUFFER CORE
1. 25.1 OVERVIEW
2. 25.2 FRAME BUFFER CORE
3. 25.3 DRIVER AND TEST PROGRAM
4. 25.4 PROJECT IDEAS
5. 25.5 BIBLIOGRAPHIC NOTES
6. 25.6 SUGGESTED EXPERIMENTS

PART V: EPILOGUE

CHAPTER 26: WHAT’S NEXT
REFERENCES
APPENDIX A: TUTORIALS
1. A.1 OVERVIEW OF XILINX VIVADO IDE
2. A.2 SHORT TUTORIAL ON VIVADO HARDWARE DEVELOPMENT
3. A.3 SHORT TUTORIAL ON VIVADO SIMULATION
4. A.4 TUTORIAL ON IP INSTANTIATION
5. A.5 SHORT TUTORIAL ON FPRO SYSTEM DEVELOPMENT
6. A.6 BIBLIOGRAPHIC NOTES

INDEX

EULA

List of Illustrations

Chapter 1

Figure 1.1 Subset covered in the book.
Figure 1.2 Graphical representation of a comparator program.
Figure 1.3 Illustration of a two-dimensional array.
Figure 1.4 Construction of a 2-bit comparator from 1-bit comparators.
Figure 1.5 Low-level diagram of a 1-bit comparator.
Figure 1.6 Testbench for a 2-bit comparator.
Figure 1.7 Simulated waveforms.

Chapter 2

Figure 2.1 Conceptual structure of an FPGA device.
Figure 2.2 Nexys 4 DDR board.
Figure 2.3 Development flow.
Figure 2.4 Vivado window.

Chapter 3

Figure 3.1 Symbol and functional table of a tristate buffer.
Figure 3.2 Wire driven by multiple circuits.
Figure 3.3 Single-buffer bidirectional I/O port.
Figure 3.4 Comparison of procedural and continuous assignments.
Figure 3.5 Implementation of an if statement.
Figure 3.6 Implementation of a parallel case statement.
Figure 3.7 Reduced-xor circuit.
Figure 3.8 Seven-segment LED display and hexadecimal patterns.
Figure 3.9 LED time-multiplexing module and decoder testing circuit.
Figure 3.10 Sign-magnitude adder testing circuit.
Figure 3.11 Floating-point addition examples.

Chapter 4

Figure 4.1 Block diagram and functional table of a D FF.
Figure 4.2 Block diagram of a synchronous system.
Figure 4.3 D FF with synchronous enable.
Figure 4.4 Testbench waveform.
Figure 4.5 Time-multiplexed seven-segment LED display.
Figure 4.6 Timing diagram of a time-multiplexed seven-segment LED display.
Figure 4.7 Symbol and block diagram of a time-multiplexing circuit.
Figure 4.8 LED time-multiplexing testing circuit.
Figure 4.9 Block diagram of a hexadecimal time-multiplexing circuit.
Figure 4.10 Timing diagram of a D FF.
Figure 4.11 Area-delay trade-off curve.
Figure 4.12 Conceptual clock tree.
Figure 4.13 Pattern for Experiment 4.8.3.
Figure 4.14 Pattern for Experiment 4.8.4.

Chapter 5

Figure 5.1 Block diagram of a synchronous FSM.
Figure 5.2 Symbol of a state.
Figure 5.3 Example of an FSM.
Figure 5.4 Edge detector based on a Moore machine.
Figure 5.5 Timing diagram of two edge detectors.
Figure 5.6 Edge detector based on a Mealy machine.
Figure 5.7 Gate-level implementation of an edge detector.
Figure 5.8 Original and debounced waveforms.
Figure 5.9 State diagram of a debouncing circuit.
Figure 5.10 Debouncing testing circuit.
Figure 5.11 Conceptual diagram of gate sensors.

Chapter 6

Figure 6.1 Block and timing diagrams of an RT operation.
Figure 6.2 Realization of an ASMD segment.
Figure 6.3 Realization of an RT operation in a conditional output box.
Figure 6.4 ASM block affected by a delayed store.
Figure 6.5 Block diagram of an FSMD.
Figure 6.6 ASMD chart of a debouncing circuit.
Figure 6.7 ASMD segment with sharing opportunity.
Figure 6.8 ASMD chart of a Fibonacci circuit.
Figure 6.9 Long division of two 4-bit unsigned integers.
Figure 6.10 Sketch of division circuit’s data path.
Figure 6.11 ASMD chart of a period counter.
Figure 6.12 Accurate low-frequency counter.

Chapter 7

Figure 7.1 Block diagram of a four-word register file.
Figure 7.2 Conceptual diagram of a FIFO buffer.
Figure 7.3 FWFT FIFO buffer conversion.
Figure 7.4 FIFO buffer based on a circular queue.
Figure 7.5 Block diagram of a register file based FIFO buffer.
Figure 7.6 Tri-port RAM constructed with two dual-port RAM.
Figure 7.7 Conceptual diagram of an SDRAM controller.

Chapter 8

Figure 8.1 Simulation timing model.
Figure 8.2 Circuits inferred by mixed assignment.
Figure 8.3 Four-bit binary wheel.

Chapter 9

Figure 9.1 IP-centered SoC development flow.
Figure 9.2 Top-level diagram of an FPro system.
Figure 9.3 Software hierarchy of an FPro SoC system.
Figure 9.4 FPro SoC development flow.
Figure 9.5 Vanilla FPro system.

Chapter 10

Figure 10.1 Software hierarchy.
Figure 10.2 Address map of a simple system.
Figure 10.3 I/O register map of a timer core.
Figure 10.4 Snapshots of pointer operation.
Figure 10.5 An I/O register with three fields.
Figure 10.6 Include file hierarchy.

Chapter 11

Figure 11.1 Conceptual bus diagram.
Figure 11.2 Timing diagram of the FPro bus.
Figure 11.3 Block diagram of the write interface.
Figure 11.4 Block diagram of the read interface.
Figure 11.5 Write interface with FIFO buffers.
Figure 11.6 Read interface with FIFO buffers.
Figure 11.7 Block diagram of the MMIO controller.
Figure 11.8 Vanilla FPro system.
Figure 11.9 Representative timing diagram of MCS I/O bus.

Chapter 12

Figure 12.1 Transmission of a byte.
Figure 12.2 Block diagram of a complete UART.
Figure 12.3 ASMD chart of a UART receiver.
Figure 12.4 Layered model of an emulated serial port.

Chapter 13

Figure 13.1 Conceptual block diagram of XADC.
Figure 13.2 Block diagram of the XADC core wrapping circuit.
Figure 13.3 Analog input pin arrangement of Nexys 4 DDR JXADC PMOD port.
Figure 13.4 Voltage divider for an analog input.

Chapter 14

Figure 14.1 Definition and examples of duty cycle.
Figure 14.2 Block diagram of a basic PWM circuit.
Figure 14.3 Servo motor.
Figure 14.4 Servo motor timing diagram.
Figure 14.5 “Rainbow” spectrum.

Chapter 15

Figure 15.1 Seven-segment LED display and hexadecimal patterns.
Figure 15.2 An 8-by-8 LED matrix.
Figure 15.3 LED matrix diagram.

Chapter 16

Figure 16.1 Conceptual diagram of the SPI bus.
Figure 16.2 Multiple-slave configuration.
Figure 16.3 Representative timing diagram of an SPI data transfer.
Figure 16.4 SPI modes.
Figure 16.5 Timing with an ss_n signal.
Figure 16.6 Timing of data shift operation.
Figure 16.7 SPI controller ASMD chart.
Figure 16.8 ADXL362 read and write transactions.
Figure 16.9 Protocol to read a data block in SPI mode.

Chapter 17

Figure 17.1 Conceptual diagram of I²C bus.
Figure 17.2 Conceptual sequence of reading and writing two bytes of data.
Figure 17.3 Timing diagram of an I²C write transaction.
Figure 17.4 State division of I²C transactions.
Figure 17.5 Sketch of an I²C controller FSM.
Figure 17.6 Conceptual diagram of output control logic.
Figure 17.7 Top-level diagram of I²C controller.
Figure 17.8 ADT7420 read operation.
Figure 17.9 Wii Nunchuk and adaptor.

Chapter 18

Figure 18.1 PS2-device-to-host timing diagram of a PS2 port.
Figure 18.2 Host-to-PS2-device timing diagram of a PS2 port.
Figure 18.3 Block diagram of a complete PS2 controller.
Figure 18.4 ASMD chart of the PS2 port receiver.
Figure 18.5 Tristate buffers of the PS2 transmission subsystem.
Figure 18.6 ASMD chart of the PS2 transmitting subsystem.
Figure 18.7 Scan code of the PS2 keyboard.

Chapter 19

Figure 19.1 Block diagram for synthesizing a digital waveform.
Figure 19.2 Block diagram for synthesizing an analog waveform.
Figure 19.3 Block diagram for synthesizing a modulated analog waveform.
Figure 19.4 Input and output of a PDM circuit.
Figure 19.5 Conceptual block diagram of a one-bit delta-sigma DAC.

Chapter 20

Figure 20.1 ADSR envelope for a piano.
Figure 20.2 ASMD chart of ADSR circuit.

Chapter 21

Figure 21.1 Display screen.
Figure 21.2 Flow control conceptual diagrams.
Figure 21.3 Periodic data streams versus burst data streams.
Figure 21.4 Conceptual diagram of a CRT monitor.
Figure 21.5 CRT scanning pattern.
Figure 21.6 Timing diagram of a horizontal scan (with VGA resolution).
Figure 21.7 Timing diagram of a vertical scan (with VGA resolution).
Figure 21.8 Conceptual block diagram of the VGA synchronization circuit.
Figure 21.9 Bar testing screen.
Figure 21.10 Block diagram of the demo video system.

Chapter 22

Figure 22.1 Top-level diagram of an FPro system
Figure 22.2 Two types of FPro video core.
Figure 22.3 Chroma-key demonstration.
Figure 22.4 Block diagram of an FPro video core.
Figure 22.5 Conceptual diagram of the video synchronization core.
Figure 22.6 Simplified synchronization FSM state diagram.
Figure 22.7 Conceptual pipelined video subsystem.
Figure 22.8 Conceptual diagram of the highlight core.

Chapter 23

Figure 23.1 Mouse pointer sprite.
Figure 23.2 Block diagram of a sprite generation circuit.
Figure 23.3 In-region comparison screen.
Figure 23.4 Ghost sprites.
Figure 23.5 LED sprites.

Chapter 24

Figure 24.1 Tile-based waveform screen.
Figure 24.2 Font pattern for the letter A.
Figure 24.3 Conceptual block diagram of the OSD pixel generation circuit.

Chapter 25

Figure 25.1 Top-level diagram of the frame buffer pixel generation circuit.
Figure 25.2 OV7670 camera module.
Figure 25.3 Block diagram of OV7670 and camera core.

Appendix

Figure A.1 Typical Vivado window.
Figure A.2 Flow Navigator subwindow.
Figure A.3 Typical source subwindow.
Figure A.4 Complete simulation window.
Figure A.5 Initial simulation window.
Figure A.6 BRAM-based dual-clock FIFO template window.
Figure A.7 MicroBlaze MCS configuration window.
Figure A.8 MicroBlaze .veo file.
Figure A.9 Basic page of XADC Wizard.
Figure A.10 Channel Sequencer page of XADC Wizard
Figure A.11 Output Clocks page of MMCM Wizard
Figure A.12 Xilinx SDK.
Figure A.13 BSP dialog.
Figure A.14 New project dialog.
Figure A.15 Project Explorer subwindow.
Figure A.16 File size information.
Figure A.17 PuTTY screen.

PREFACE

HDL (hardware description language) and FPGA (field-programmable gate array) devices allow designers to quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify operation of the physical implementation. As the capacity of FPGA devices continues to grow, a device can accommodate an SoC (system on a chip) design, which integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single chip. This book uses a “learning by doing” approach and illustrates the FPGA and HDL development and design process by a series of examples in the SoC context.

The examples start with simple gate-level circuits, progress gradually through the RT (register-transfer) level modules, and lead to a functional embedded system with custom I/O peripherals and hardware accelerators. A simple SoC framework, FPro (abbreviated from the book title “FPGA Prototyping”), is introduced as a platform to integrate all the design examples together. An FPro system contains a Xilinx MicroBlaze MCS soft-core processor, a video subsystem, and the MMIO (memory-mapped I/O) subsystem that can incorporate custom I/O cores. Except for the processor, all components are designed and coded from scratch. All the hardware and software examples can be synthesized, compiled, and physically tested on the prototyping board.

Focus and audience

Focus The primary focus of this book is on developing efficient and reliable digital systems and effectively using HDL as a tool to describe the intended hardware. The HDL language itself is not the main subject and its coverage is limited to a small synthesizable subset. The book uses about a dozen proven code templates to provide the skeletal structures of various types of circuits. These templates are general and can easily be integrated to construct a large, complex system. Although this approach limits the “freedom” of syntactic expression, it helps us steer our effort to develop an innovative and efficient hardware architecture.

After discussing the fundamentals in Part I, the book illustrates more complicated and sophisticated designs in the SoC context. Along the way, readers will learn many system-level concepts, including the derivation of a soft-core processor and IP (intellectual property) core based system, the partition and integration of software and hardware, and the development of custom I/O peripherals and hardware accelerators.

Although the book is intended for beginning designers, the examples follow strict design guidelines and prepare readers for future endeavors. The coding and design practice is “forward compatible,” by which we mean the following:

The same practice can be applied to large designs in the future.
The same practice can aid other system development tasks, including simulation, timing analysis, verification, and testing.
The same practice can be applied to ASIC technology and different types of FPGA devices.
The code can be accepted by synthesis software from different vendors.

Audience and prerequisites

The intended audience is students in an advanced digital design course as well as practicing engineers who wish to learn FPGA-and HDL-based developments. Readers need to have a basic knowledge of digital systems, usually a required course in electrical engineering and computer engineering curricula, and a working knowledge of the C/C++ language. Prior exposure to computer architecture, embedded system, and operating system is not necessary but will be helpful.

Changes for the MicroBlaze MCS SoC Edition

This book is the successor edition of FPGA Prototyping by Verilog Examples: Xilinx Spartan 3 Version. The System Verilog in the title reflects the fact that the book uses the new language constructs of SystemVerilog. The most significant change is that the new edition presents the hardware in the SoC context and covers many system-level concepts. Instead of treating each module as an isolated entity, the book integrates them into a single coherent SoC platform that allows readers to explore both hardware and software “programmability” and develop complex and interesting embedded system projects. The major revisions in this edition are the following:

Add four general-purpose peripheral modules: multi-channel PWM (pulse width modulation), I2C controller, SPI controller, and XADC (Xilinx analog-to-digital converter) controller.
Introduce a music synthesizer constructed with a DDFS (direct digital frequency synthesis) module and an ADSR (attack-decay-sustain-release) envelope generator.
Expand the original video controller into a complete stream-based video subsystem that incorporates a video synchronization circuit, a test-pattern generator, an OSD (on-screen-display) controller, a sprite generator, and a frame buffer.
Expand the coverage of timing model and provide an in-depth discussion of blocking and nonblocking statements.
Introduce basic concepts of software-hardware co-design with Xilinx Micro-Blaze MCS soft-core processor.
Provide an overview of the bus interconnect and interface circuit.
Introduce basic embedded system software development.
Suggest additional modules and peripherals for interesting and challenging projects.

Logistics

FPGA prototyping board

This book is prepared to be used with the Nexys 4 DDR FPGA prototyping board manufactured by Digilent Inc. It contains an Artix FPGA device and the needed I/O peripherals. All HDL codes and discussions of this book can be applied to this board directly. The less expensive Basys 3 board can be used as well. This board incorporates fewer I/O peripherals and contains a smaller FPGA device.

Most peripherals discussed in the book are de facto industrial standards and the corresponding HDL codes can be used for other FPGA boards as long as they provide adequate analog interface circuits and connectors. Another option is to use stand-alone I/O peripheral modules or to construct the circuits on a breadboard.

Software

The book uses the Xilinx Vivado WebPack edition for hardware development and Xilinx SDK for software development. Both software packages are free and can be downloaded from Xilinx’s website.

PC accessories

The design examples involve interfaces to several PC peripheral devices, including a USB keyboard, a USB mouse, a VGA compatible monitor, and a powered speaker. These accessories are widely available and probably can be obtained from an old PC.

Book organization

The book is divided into four major parts. Part I introduces the elementary HDL constructs and their hardware counterparts, and demonstrates the construction of a basic digital circuit with these constructs. It consists of six chapters:

Chapter 1 describes the skeleton of an HDL program, the basic language syntax, and the logical operators. Gate-level combinational circuits are derived with these language constructs.
Chapter 2 provides an overview of an FPGA device, prototyping board, and development flow.
Chapter 3 introduces HDL’s relational and arithmetic operators and routing constructs. These correspond to medium-sized components, such as comparators, adders, and multiplexers. Module-level combinational circuits are derived with these language constructs.
Chapter 4 presents the codes for memory elements and the construction of “regular” sequential circuits, such as counters and shift registers, in which the state transitions exhibit a regular pattern.
Chapter 5 discusses the construction of a finite state machine (FSM), which is a sequential circuit whose state transitions do not exhibit a simple, regular pattern.
Chapter 6 presents the construction of an FSM with data path (FSMD). The FSMD is used to implement the register-transfer (RT) methodology, in which the system operation is described by data transfers and manipulations among registers.
Chapter 7 covers the methods to infer FPGA’s internal memory modules, which can then be used to construct buffers and lookup tables.
Chapter 8 provides an in-depth coverage of the timing model and data types and discusses an alternate coding style. This chapter can be skipped without affecting the remaining chapters.

Part II introduces the hardware construction of an FPro system and the development of embedded software. A basic “vanilla” FPro system, which contains a timer core, a UART (universal asynchronous receiver and transmitter) core, a GPI (general-purpose input) core, and a GPO (general-purpose output) core, is used to illustrate the key concepts of the process. It consists of four chapters:

Chapter 9 introduces the SoC development and provides an overview of the hardware organization and software structure of the FPro platform.
Chapter 10 discusses the software development for an embedded system and the basic coding techniques to access low-level I/O cores.
Chapter 11 covers the FPro bus protocol and the bus interface circuit and demonstrates the construction of basic GPI, GPO, and timer cores.
Chapter 12 presents the construction of a more sophisticated UART core and the derivation of software device drivers.

Part III applies the techniques from Parts I and II to develop an array of I/O cores for the peripherals on the Nexys 4 DDR prototyping board. The I/O cores are constructed from scratch with custom hardware and device driver. Part III consists of nine chapters:

Chapter 13 discusses the Xilinx device’s internal analog-to-digital converter (XADC) and derives an interface circuit to retrieve the analog readings.
Chapter 14 presents the design of a multi-channel PWM core and demonstrates its application for LED brightness adjustment and servo motor control.
Chapter 15 converts the seven-segment LED control circuit and the switch debouncing circuit of Part I into I/O cores and integrates them into an FPro system.
Chapter 16 provides an overview of the SPI protocol, covers the design of an SPI controller core, and shows its operation with Nexys 4 DDR board’s ADXL362 three-axis accelerometer.
Chapter 17 provides an overview of the I2C protocol, discusses the design of an I2C controller core, and demonstrates its operation with Nexys 4 DDR board’s ADT7420 temperature sensor.
Chapter 18 covers the design of a PS2 controller core, which can be connected to a PS2 mouse or a PS2 keyboard, and discusses the device driver routines to read and decode keyboard scan codes and to obtain and process mouse movement information and button activities.
Chapter 19 discusses the construction of a DDFS (direct digital frequency synthesis) controller core with amplitude and frequency modulation and demonstrates its application as a music synthesizer.
Chapter 20 augments the music synthesizer with an ADSR (attack-decaysustain-release) envelope generator core, which can produce sound mimicking various music instruments.

Part IV discusses the development of a stream-based video subsystem. The subsystem provides a framework to generate and mix multiple video sources into a single video data stream for display. It consists of four chapters:

Chapter 21 introduces the concept of stream data processing and constructs a basic video system with a test-pattern generator, a color-to-grayscale conversion circuit, and a frame synchronization circuit.
Chapter 22 provides an overview of the FPro video subsystem framework and the FPro video core structure and demonstrates the stream interface with a line buffer.
Chapter 23 presents the design of a sprite circuit, which adds an overlay of small animated objects on the screen, and applies the technique for a mouse pointer core and a “Pac-Man ghost character” core.
Chapter 24 discusses the design of an OSD (on-screen-display) controller core, which produces an overlay of text similar to the subtitles on a TV screen.
Chapter 25 covers the design of a frame buffer, which maintains a bitmap for one screen.

In addition to the main text chapters, the book includes an Appendix with four tutorials. The tutorials consist of the following:

Develop, synthesize, and implement a digital circuit on the Nexys 4 DDR board with Vivado.
Perform simulation of an HDL program with Vivado’s built-in simulator.
Configure and instantiate Xilinx IP cores.
Construct a basic FPro system with a Xilinx microBlaze MCS IP core and develop software with the Xilinx SDK platform.

Companion Website

On an accompanying website (http://academic.csuohio.edu/chu_p) additional information is available, including the following materials:

Errata
HDL and C/C++ code listings and relevant files
Links to synthesis and simulation software
Links to reference materials

The printed book contains a number of color figures. They are shown as grayscale in the printed version. These figures can be found in full color on the website as well.

Errata

The book is self-prepared, which means that the author has produced all aspects of the text, including illustrations, tables, code listings, indexing, and formatting. As errors are always bound to happen, the accompanying website provides an updated errata sheet and a place to report errors.

P. P. CHU

Cleveland, Ohio
February 2018

FPGA PROTOTYPING BY SYSTEMVERILOG EXAMPLES

Xilinx MicroBlaze MCS SoC Edition